3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
7 * hacked for Hymod FPGA support by Murray.Jensen@csiro.au, 29-Jan-01
13 #include <asm/iopin_8260.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 /*-----------------------------------------------------------------------
18 * Board Special Commands: FPGA load/store, EEPROM erase
21 #if defined(CONFIG_CMD_BSP)
23 #define LOAD_SUCCESS 0
24 #define LOAD_FAIL_NOCONF 1
25 #define LOAD_FAIL_NOINIT 2
26 #define LOAD_FAIL_NODONE 3
28 #define STORE_SUCCESS 0
31 * Programming the Hymod FPGAs
33 * The 8260 io port config table is set up so that the INIT pin is
34 * held Low (Open Drain output 0) - this will delay the automatic
35 * Power-On config until INIT is released (by making it an input).
37 * If the FPGA has been programmed before, then the assertion of PROGRAM
38 * will initiate configuration (i.e. it begins clearing the RAM).
40 * When the FPGA is ready to receive configuration data (either after
41 * releasing INIT after Power-On, or after asserting PROGRAM), it will
44 * Notes from Paul Dunn:
46 * 1. program pin should be forced low for >= 300ns
47 * (about 20 bus clock cycles minimum).
49 * 2. then wait for init to go high, which signals
50 * that the FPGA has cleared its internal memory
51 * and is ready to load
53 * 3. perform load writes of entire config file
55 * 4. wait for done to go high, which should be
56 * within a few bus clock cycles. If done has not
57 * gone high after reasonable period, then load
58 * has not worked (wait several ms?)
62 fpga_load(int mezz, const uchar *addr, ulong size)
64 hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
67 volatile uchar *fpgabase;
69 const uchar *eaddr = addr + size;
73 fp = &cp->mezz.xlx[0];
75 fp = &cp->main.xlx[0];
77 if (!fp->mmap.prog.exists)
78 return (LOAD_FAIL_NOCONF);
80 fpgabase = (uchar *)fp->mmap.prog.base;
83 /* set enable HIGH if required */
84 if (fpgaio->enable_pin.flag)
85 iopin_set_high (&fpgaio->enable_pin);
87 /* ensure INIT is released (set it to be an input) */
88 iopin_set_in (&fpgaio->init_pin);
90 /* toggle PROG Low then High (will already be Low after Power-On) */
91 iopin_set_low (&fpgaio->prog_pin);
92 udelay (1); /* minimum 300ns - 1usec should do it */
93 iopin_set_high (&fpgaio->prog_pin);
95 /* wait for INIT High */
97 while (!iopin_is_high (&fpgaio->init_pin))
98 if (++cnt == 10000000) {
99 result = LOAD_FAIL_NOINIT;
103 /* write configuration data */
107 /* wait for DONE High */
109 while (!iopin_is_high (&fpgaio->done_pin))
110 if (++cnt == 100000000) {
111 result = LOAD_FAIL_NODONE;
116 result = LOAD_SUCCESS;
120 if (fpgaio->enable_pin.flag)
121 iopin_set_low (&fpgaio->enable_pin);
126 /* ------------------------------------------------------------------------- */
128 do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
130 uchar *addr, *save_addr;
132 int mezz, arg, result;
141 if (strcmp (argv[1], "info") == 0) {
142 printf ("\nHymod FPGA Info...\n");
143 printf ("\t\t\t\tAddress\t\tSize\n");
144 printf ("\tMain Configuration:\t0x%08x\t%d\n",
145 FPGA_MAIN_CFG_BASE, FPGA_MAIN_CFG_SIZE);
146 printf ("\tMain Register:\t\t0x%08x\t%d\n",
147 FPGA_MAIN_REG_BASE, FPGA_MAIN_REG_SIZE);
148 printf ("\tMain Port:\t\t0x%08x\t%d\n",
149 FPGA_MAIN_PORT_BASE, FPGA_MAIN_PORT_SIZE);
150 printf ("\tMezz Configuration:\t0x%08x\t%d\n",
151 FPGA_MEZZ_CFG_BASE, FPGA_MEZZ_CFG_SIZE);
157 if (strcmp (argv[1], "store") == 0) {
158 addr = (uchar *) simple_strtoul (argv[2], NULL, 16);
162 /* fpga readback unimplemented */
163 while (more readback data)
165 result = error ? STORE_FAIL_XXX : STORE_SUCCESS;
167 result = STORE_SUCCESS;
170 if (result == STORE_SUCCESS) {
171 printf ("SUCCEEDED (%d bytes)\n",
175 printf ("FAILED (%d bytes)\n",
182 if (strcmp (argv[1], "tftp") == 0) {
183 copy_filename (BootFile, argv[2], sizeof (BootFile));
184 load_addr = simple_strtoul (argv[3], NULL, 16);
185 NetBootFileXferSize = 0;
187 if (NetLoop(TFTPGET) <= 0) {
188 printf ("tftp transfer failed - aborting "
193 if (NetBootFileXferSize == 0) {
194 printf ("can't determine file size - "
195 "aborting fpga load\n");
199 printf ("File transfer succeeded - "
200 "beginning fpga load...");
202 result = fpga_load (0, (uchar *) load_addr,
203 NetBootFileXferSize);
205 if (result == LOAD_SUCCESS) {
206 printf ("SUCCEEDED\n");
208 } else if (result == LOAD_FAIL_NOCONF)
209 printf ("FAILED (no CONF)\n");
210 else if (result == LOAD_FAIL_NOINIT)
211 printf ("FAILED (no INIT)\n");
213 printf ("FAILED (no DONE)\n");
217 /* fall through ... */
220 if (strcmp (argv[1], "load") == 0) {
222 if (strcmp (argv[2], "main") == 0)
224 else if (strcmp (argv[2], "mezz") == 0)
227 printf ("FPGA type must be either "
228 "`main' or `mezz'\n");
237 addr = (uchar *) simple_strtoul (argv[arg++], NULL, 16);
238 size = (ulong) simple_strtoul (argv[arg], NULL, 16);
240 result = fpga_load (mezz, addr, size);
242 if (result == LOAD_SUCCESS) {
243 printf ("SUCCEEDED\n");
245 } else if (result == LOAD_FAIL_NOCONF)
246 printf ("FAILED (no CONF)\n");
247 else if (result == LOAD_FAIL_NOINIT)
248 printf ("FAILED (no INIT)\n");
250 printf ("FAILED (no DONE)\n");
259 return cmd_usage(cmdtp);
264 "load [type] addr size\n"
265 " - write the configuration data at memory address `addr',\n"
266 " size `size' bytes, into the FPGA of type `type' (either\n"
267 " `main' or `mezz', default `main'). e.g.\n"
268 " `fpga load 100000 7d8f'\n"
269 " loads the main FPGA with config data at address 100000\n"
270 " HEX, size 7d8f HEX (32143 DEC) bytes\n"
271 "fpga tftp file addr\n"
272 " - transfers `file' from the tftp server into memory at\n"
273 " address `addr', then writes the entire file contents\n"
274 " into the main FPGA\n"
276 " - read configuration data from the main FPGA (the mezz\n"
277 " FPGA is write-only), into address `addr'. There must be\n"
278 " enough memory available at `addr' to hold all the config\n"
279 " data - the size of which is determined by VC:???\n"
281 " - print information about the Hymod FPGA, namely the\n"
282 " memory addresses at which the four FPGA local bus\n"
283 " address spaces appear in the physical address space"
285 /* ------------------------------------------------------------------------- */
287 do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
289 uchar data[HYMOD_EEPROM_SIZE];
290 uint addr = CONFIG_SYS_I2C_EEPROM_ADDR;
295 addr |= HYMOD_EEOFF_MAIN;
299 if (strcmp (argv[1], "main") == 0) {
300 addr |= HYMOD_EEOFF_MAIN;
303 if (strcmp (argv[1], "mezz") == 0) {
304 addr |= HYMOD_EEOFF_MEZZ;
307 /* fall through ... */
310 return cmd_usage(cmdtp);
313 memset (data, 0, HYMOD_EEPROM_SIZE);
315 eeprom_write (addr, 0, data, HYMOD_EEPROM_SIZE);
320 eeclear, 1, 0, do_eecl,
321 "Clear the eeprom on a Hymod board",
323 " - write zeroes into the EEPROM on the board of type `type'\n"
324 " (`type' is either `main' or `mezz' - default `main')\n"
325 " Note: the EEPROM write enable jumper must be installed"
328 /* ------------------------------------------------------------------------- */
331 do_htest (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
336 #ifdef CONFIG_ETHER_LOOPBACK_TEST
337 extern void eth_loopback_test (void);
338 #endif /* CONFIG_ETHER_LOOPBACK_TEST */
340 printf ("HYMOD tests - ensure loopbacks etc. are connected\n\n");
343 /* Load FPGA with test program */
345 printf ("Loading test FPGA program ...");
347 rc = fpga_load (0, test_bitfile, sizeof (test_bitfile));
352 printf (" SUCCEEDED\n");
355 case LOAD_FAIL_NOCONF:
356 printf (" FAILED (no configuration space defined)\n");
359 case LOAD_FAIL_NOINIT:
360 printf (" FAILED (timeout - no INIT signal seen)\n");
363 case LOAD_FAIL_NODONE:
364 printf (" FAILED (timeout - no DONE signal seen)\n");
368 printf (" FAILED (unknown return code from fpga_load\n");
372 /* run Local Bus <=> Xilinx tests */
374 /* tell Xilinx to run ZBT Ram, High Speed serial and Mezzanine tests */
379 #ifdef CONFIG_ETHER_LOOPBACK_TEST
380 /* run Ethernet test */
381 eth_loopback_test ();
382 #endif /* CONFIG_ETHER_LOOPBACK_TEST */