3 * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/iopin_8260.h>
16 * hymod configuration data - passed by boot code via the board information
17 * structure (only U-Boot has support for this at the moment)
19 * there are three types of data passed up from the boot monitor. the first
20 * (type hymod_eeprom_t) is the eeprom data that was read off both the main
21 * (or mother) board and the mezzanine board (if any). this data defines how
22 * many Xilinx fpgas are on each board, and their types (among other things).
23 * the second type of data (type xlx_mmap_t, one per Xilinx fpga) defines where
24 * in the physical address space the various Xilinx fpga access regions have
25 * been mapped by the boot rom. the third type of data (type xlx_iopins_t,
26 * one per Xilinx fpga) defines which io port pins are connected to the various
27 * signals required to program a Xilinx fpga.
29 * A ram/flash "bank" refers to memory controlled by the same chip select.
31 * the eeprom contents are defined as in technical note #2 - basically,
32 * a header, zero or more records in no particular order, and a 32 bit crc
33 * a record is 1 or more type bytes, a length byte and "length" bytes.
36 #define HYMOD_EEPROM_ID 0xAA /* eeprom id byte */
37 #define HYMOD_EEPROM_VER 1 /* eeprom contents version (0-127) */
38 #define HYMOD_EEPROM_SIZE 256 /* number of bytes in the eeprom */
43 unsigned char id; /* eeprom id byte */
45 unsigned char ver:7; /* eeprom contents version number */
46 unsigned long len; /* total # of bytes btw hdr and crc */
50 /* maximum number of bytes available for eeprom data records */
51 #define HYMOD_EEPROM_MAXLEN (HYMOD_EEPROM_SIZE \
52 - sizeof (hymod_eehdr_t) \
53 - sizeof (unsigned long))
55 /* eeprom data record */
59 unsigned char topbit:1;
62 unsigned char data[1]; /* variable length */
65 unsigned short topbit:1;
66 unsigned short nxtbit:1;
67 unsigned short type:14;
69 unsigned char data[1]; /* variable length */
72 unsigned long topbit:1;
73 unsigned long nxtbit:1;
74 unsigned long type:30;
76 unsigned char data[1]; /* variable length */
81 #define HYMOD_EEOFF_MAIN 0x00 /* i2c addr offset for main eeprom */
82 #define HYMOD_EEOFF_MEZZ 0x04 /* i2c addr offset for mezz eepomr */
84 /* eeprom record types */
85 #define HYMOD_EEREC_SERNO 1 /* serial number */
86 #define HYMOD_EEREC_DATE 2 /* date */
87 #define HYMOD_EEREC_BATCH 3 /* batch id */
88 #define HYMOD_EEREC_TYPE 4 /* board type */
89 #define HYMOD_EEREC_REV 5 /* revision number */
90 #define HYMOD_EEREC_SDRAM 6 /* sdram sizes */
91 #define HYMOD_EEREC_FLASH 7 /* flash sizes */
92 #define HYMOD_EEREC_ZBT 8 /* zbt ram sizes */
93 #define HYMOD_EEREC_XLXTYP 9 /* Xilinx fpga types */
94 #define HYMOD_EEREC_XLXSPD 10 /* Xilinx fpga speeds */
95 #define HYMOD_EEREC_XLXTMP 11 /* Xilinx fpga temperatures */
96 #define HYMOD_EEREC_XLXGRD 12 /* Xilinx fpga grades */
97 #define HYMOD_EEREC_CPUTYP 13 /* Motorola CPU type */
98 #define HYMOD_EEREC_CPUSPD 14 /* CPU speed */
99 #define HYMOD_EEREC_BUSSPD 15 /* bus speed */
100 #define HYMOD_EEREC_CPMSPD 16 /* CPM speed */
101 #define HYMOD_EEREC_HSTYPE 17 /* high-speed serial chip type */
102 #define HYMOD_EEREC_HSCHIN 18 /* high-speed serial input channels */
103 #define HYMOD_EEREC_HSCHOUT 19 /* high-speed serial output channels */
105 /* some dimensions */
106 #define HYMOD_MAX_BATCH 32 /* max no. of bytes in batch id */
107 #define HYMOD_MAX_SDRAM 4 /* max sdram "banks" on any board */
108 #define HYMOD_MAX_FLASH 4 /* max flash "banks" on any board */
109 #define HYMOD_MAX_ZBT 16 /* max ZBT rams on any board */
110 #define HYMOD_MAX_XLX 4 /* max Xilinx fpgas on any board */
112 #define HYMOD_MAX_BYTES 16 /* enough to store any bytes array */
115 #define HYMOD_BDTYPE_NONE 0 /* information not present */
116 #define HYMOD_BDTYPE_IO 1 /* I/O main board */
117 #define HYMOD_BDTYPE_CLP 2 /* CLP main board */
118 #define HYMOD_BDTYPE_DSP 3 /* DSP main board */
119 #define HYMOD_BDTYPE_INPUT 4 /* video input mezzanine board */
120 #define HYMOD_BDTYPE_ALTINPUT 5 /* video input mezzanine board */
121 #define HYMOD_BDTYPE_DISPLAY 6 /* video display mezzanine board */
122 #define HYMOD_BDTYPE_MAX 7 /* first invalid value */
124 /* Xilinx fpga types */
125 #define HYMOD_XTYP_NONE 0 /* information not present */
126 #define HYMOD_XTYP_XCV300E 1 /* Xilinx Virtex 300 */
127 #define HYMOD_XTYP_XCV400E 2 /* Xilinx Virtex 400 */
128 #define HYMOD_XTYP_XCV600E 3 /* Xilinx Virtex 600 */
129 #define HYMOD_XTYP_MAX 4 /* first invalid value */
131 /* Xilinx fpga speeds */
132 #define HYMOD_XSPD_NONE 0 /* information not present */
133 #define HYMOD_XSPD_SIX 1
134 #define HYMOD_XSPD_SEVEN 2
135 #define HYMOD_XSPD_EIGHT 3
136 #define HYMOD_XSPD_MAX 4 /* first invalid value */
138 /* Xilinx fpga temperatures */
139 #define HYMOD_XTMP_NONE 0 /* information not present */
140 #define HYMOD_XTMP_COM 1
141 #define HYMOD_XTMP_IND 2
142 #define HYMOD_XTMP_MAX 3 /* first invalid value */
144 /* Xilinx fpga grades */
145 #define HYMOD_XTMP_NONE 0 /* information not present */
146 #define HYMOD_XTMP_NORMAL 1
147 #define HYMOD_XTMP_ENGSAMP 2
148 #define HYMOD_XTMP_MAX 3 /* first invalid value */
151 #define HYMOD_CPUTYPE_NONE 0 /* information not present */
152 #define HYMOD_CPUTYPE_MPC8260 1 /* Motorola MPC8260 embedded powerpc */
153 #define HYMOD_CPUTYPE_MAX 2 /* first invalid value */
155 /* CPU/BUS/CPM clock speeds */
156 #define HYMOD_CLKSPD_NONE 0 /* information not present */
157 #define HYMOD_CLKSPD_33MHZ 1
158 #define HYMOD_CLKSPD_66MHZ 2
159 #define HYMOD_CLKSPD_100MHZ 3
160 #define HYMOD_CLKSPD_133MHZ 4
161 #define HYMOD_CLKSPD_166MHZ 5
162 #define HYMOD_CLKSPD_200MHZ 6
163 #define HYMOD_CLKSPD_MAX 7 /* first invalid value */
165 /* high speed serial chip types */
166 #define HYMOD_HSSTYPE_NONE 0 /* information not present */
167 #define HYMOD_HSSTYPE_AMCC52064 1
168 #define HYMOD_HSSTYPE_MAX 2 /* first invalid value */
170 /* a date (yyyy-mm-dd) */
179 /* describes a Xilinx fpga */
182 unsigned char type; /* chip type */
183 unsigned char speed; /* chip speed rating */
184 unsigned char temp; /* chip temperature rating */
185 unsigned char grade; /* chip grade */
189 /* describes a Motorola embedded processor */
192 unsigned char type; /* CPU type */
193 unsigned char cpuspd; /* speed of the PowerPC core */
194 unsigned char busspd; /* speed of the system and 60x bus */
195 unsigned char cpmspd; /* speed of the CPM co-processor */
199 /* info about high-speed (1Gbit) serial interface */
202 unsigned char type; /* high-speed serial chip type */
203 unsigned char nchin; /* number of input channels mounted */
204 unsigned char nchout; /* number of output channels mounted */
209 * this defines the contents of the serial eeprom that exists on every
210 * hymod board, including mezzanine boards (the serial eeprom will be
211 * faked for early development boards that don't have one)
216 unsigned char valid:1; /* contents of this struct is valid */
217 unsigned char ver:7; /* eeprom contents version */
218 unsigned char bdtype; /* board type */
219 unsigned char bdrev; /* board revision */
220 unsigned char batchlen; /* length of batch string below */
221 unsigned long serno; /* serial number */
222 hymod_date_t date; /* manufacture date */
223 unsigned char batch[32]; /* manufacturer specific batch id */
224 unsigned char nsdram; /* # of ram "banks" */
225 unsigned char nflash; /* # of flash "banks" */
226 unsigned char nzbt; /* # of ZBT rams */
227 unsigned char nxlx; /* # of Xilinx fpgas */
228 unsigned char sdramsz[HYMOD_MAX_SDRAM]; /* log2 of sdram size */
229 unsigned char flashsz[HYMOD_MAX_FLASH]; /* log2 of flash size */
230 unsigned char zbtsz[HYMOD_MAX_ZBT]; /* log2 of ZBT ram size */
231 hymod_xlx_t xlx[HYMOD_MAX_XLX]; /* Xilinx fpga info */
232 hymod_mpc_t mpc; /* Motorola MPC CPU info */
233 hymod_hss_t hss; /* high-speed serial info */
238 * this defines a region in the processor's physical address space
242 unsigned long exists:1; /* 1 if the region exists, 0 if not */
243 unsigned long size:31; /* size in bytes */
244 unsigned long base; /* base address */
249 * this defines where the various Xilinx fpga access regions are mapped
250 * into the physical address space of the processor
254 xlx_prgn_t prog; /* program access region */
255 xlx_prgn_t reg; /* register access region */
256 xlx_prgn_t port; /* port access region */
261 * this defines which 8260 i/o port pins are connected to the various
262 * signals required for programming a Xilinx fpga
266 iopin_t prog_pin; /* assert for >= 300ns to program */
267 iopin_t init_pin; /* goes high when fpga is cleared */
268 iopin_t done_pin; /* goes high when program is done */
269 iopin_t enable_pin; /* some fpgas need enabling */
273 /* all info about one Xilinx chip */
278 unsigned long irq:8; /* h/w intr req number for this fpga */
282 /* all info about one hymod board */
285 hymod_eeprom_t eeprom;
286 xlx_info_t xlx[HYMOD_MAX_XLX];
291 * this defines the configuration information of a hymod board-set
292 * (main board + possible mezzanine board). In future, there may be
293 * more than one mezzanine board (stackable?) - if so, add a "mezz2"
294 * field, and so on... or make mezz an array?
298 unsigned long ver:8; /* version control */
299 hymod_board_t main; /* main board info */
300 hymod_board_t mezz; /* mezzanine board info */
301 unsigned long crc; /* ensures kernel and boot prom agree */
305 #endif /* _HYMOD_H_ */