2 * (C) Copyright 2000-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
11 int checkboard (void) {
12 puts ("Board: iDMR\n");
16 phys_size_t initdram (int board_type) {
20 * After reset, CS0 is configured to cover entire address space. We
21 * need to configure it to its proper values, so that writes to
22 * CONFIG_SYS_SDRAM_BASE and vicinity during SDRAM controller setup below do
23 * now fall under CS0 (see 16.3.1 of the MCF5271 Reference Manual).
26 /* Flash chipselect, CS0 */
27 /* ;CSAR0: Flash at 0xFF800000 */
28 mbar_writeShort(0x0080, 0xFF80);
30 /* CSCR0: Flash 6 waits, 16bit */
31 mbar_writeShort(0x008A, 0x1980);
33 /* CSMR0: Flash 8MB, R/W, valid */
34 mbar_writeLong(0x0084, 0x007F0001);
38 * SDRAM configuration proper
42 * Address/Data Pin Assignment Reg.: enable address lines 23-21; do
43 * not enable data pins D[15:0], as we have 16 bit port to SDRAM
45 mbar_writeByte(MCF_GPIO_PAR_AD,
50 /* No need to configure BS pins - reset values are OK */
52 /* Chip Select Pin Assignment Reg.: set CS[1-7] to GPIO */
53 mbar_writeByte(MCF_GPIO_PAR_CS, 0x00);
55 /* SDRAM Control Pin Assignment Reg. */
56 mbar_writeByte(MCF_GPIO_PAR_SDRAM,
57 MCF_GPIO_SDRAM_CSSDCS_00 | /* no matter: PAR_CS=0 */
62 MCF_GPIO_SDRAM_SDCS_01);
65 * Wait 100us. We run the bus at 50MHz, one cycle is 20ns. So 5
66 * iterations will do, but we do 10 just to be safe.
68 for (i = 0; i < 10; ++i)
72 /* 1. Initialize DRAM Control Register: DCR */
73 mbar_writeShort(MCF_SDRAMC_DCR,
74 MCF_SDRAMC_DCR_RTIM(0x10) | /* 65ns */
75 MCF_SDRAMC_DCR_RC(0x60)); /* 1562 cycles */
81 * CL: 11 (CL=3: 0x03, 0x02; CL=2: 0x1)
82 * CBM: cmd at A20, bank select bits 21 and up
85 mbar_writeLong(MCF_SDRAMC_DACR0,
86 MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18) |
87 MCF_SDRAMC_DACRn_BA(0x00) |
88 MCF_SDRAMC_DACRn_CASL(0x03) |
89 MCF_SDRAMC_DACRn_CBM(0x03) |
90 MCF_SDRAMC_DACRn_PS(0x03));
93 mbar_writeLong(MCF_SDRAMC_DMR0,
94 MCF_SDRAMC_DMRn_BAM_16M |
98 /* 3. Set IP bit in DACR to initiate PALL command */
99 mbar_writeLong(MCF_SDRAMC_DACR0,
100 mbar_readLong(MCF_SDRAMC_DACR0) |
101 MCF_SDRAMC_DACRn_IP);
103 /* Write to this block to initiate precharge */
104 *(volatile u16 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5;
107 * Wait at least 20ns to allow banks to precharge (t_RP = 20ns). We
108 * wait a wee longer, just to be safe.
110 for (i = 0; i < 5; ++i)
114 /* 4. Set RE bit in DACR */
115 mbar_writeLong(MCF_SDRAMC_DACR0,
116 mbar_readLong(MCF_SDRAMC_DACR0) |
117 MCF_SDRAMC_DACRn_RE);
120 * Wait for at least 8 auto refresh cycles to occur, i.e. at least
123 for (i = 0; i < 1000; ++i)
126 /* Finish the configuration by issuing the MRS */
127 mbar_writeLong(MCF_SDRAMC_DACR0,
128 mbar_readLong(MCF_SDRAMC_DACR0) |
129 MCF_SDRAMC_DACRn_MRS);
132 * Write to the SDRAM Mode Register A0-A11 = 0x400
134 * Write Burst Mode = Programmed Burst Length
135 * Op Mode = Standard Op
137 * Burst Type = Sequential
140 *(volatile u32 *)(CONFIG_SYS_SDRAM_BASE + 0x1800) = 0xa5a5a5a5;
142 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
146 int testdram (void) {
148 /* TODO: XXX XXX XXX */
149 printf ("DRAM test not implemented!\n");