2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
3 * Copyright (C) 2013 Imagination Technologies
5 * SPDX-License-Identifier: GPL-2.0
12 #include <pci_gt64120.h>
13 #include <pci_msc01.h>
17 #include <asm/addrspace.h>
19 #include <asm/malta.h>
35 static void malta_lcd_puts(const char *str)
38 void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
40 /* print up to 8 characters of the string */
41 for (i = 0; i < min((int)strlen(str), 8); i++) {
42 __raw_writel(str[i], reg);
43 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
46 /* fill the rest of the display with spaces */
48 __raw_writel(' ', reg);
49 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
53 static enum core_card malta_core_card(void)
57 rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION));
58 corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
61 case MALTA_REVISION_CORID_CORE_LV:
64 case MALTA_REVISION_CORID_CORE_FPGA6:
72 static enum sys_con malta_sys_con(void)
74 switch (malta_core_card()) {
76 return SYSCON_GT64120;
82 return SYSCON_UNKNOWN;
86 phys_size_t initdram(int board_type)
88 return CONFIG_SYS_MEM_SIZE;
95 malta_lcd_puts("U-boot");
96 puts("Board: MIPS Malta");
98 core = malta_core_card();
109 puts(" CoreUnknown");
116 int board_eth_init(bd_t *bis)
118 return pci_eth_init(bis);
121 void _machine_restart(void)
123 void __iomem *reset_base;
125 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
126 __raw_writel(GORESET, reset_base);
129 int board_early_init_f(void)
133 /* choose correct PCI I/O base */
134 switch (malta_sys_con()) {
136 io_base = (void *)CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
140 io_base = (void *)CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
147 /* setup FDC37M817 super I/O controller */
148 malta_superio_init(io_base);
153 int misc_init_r(void)
160 struct serial_device *default_serial_console(void)
162 switch (malta_sys_con()) {
164 return &eserial1_device;
168 return &eserial2_device;
172 void pci_init_board(void)
178 switch (malta_sys_con()) {
180 set_io_port_base(CKSEG1ADDR(MALTA_GT_PCIIO_BASE));
182 gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
183 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
184 0x10000000, 0x10000000, 128 * 1024 * 1024,
185 0x00000000, 0x00000000, 0x20000);
190 set_io_port_base(CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE));
192 msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
193 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
194 MALTA_MSC01_PCIMEM_MAP,
195 CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE),
196 MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP,
197 0x00000000, MALTA_MSC01_PCIIO_SIZE);
201 bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
202 PCI_DEVICE_ID_INTEL_82371AB_0, 0);
204 panic("Failed to find PIIX4 PCI bridge\n");
206 /* setup PCI interrupt routing */
207 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10);
208 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10);
209 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11);
210 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11);
212 /* mux SERIRQ onto SERIRQ pin */
213 pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32);
214 val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ;
215 pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32);
217 /* enable SERIRQ - Linux currently depends upon this */
218 pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
219 val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
220 pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
222 bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
223 PCI_DEVICE_ID_INTEL_82371AB, 0);
225 panic("Failed to find PIIX4 IDE controller\n");
227 /* enable bus master & IO access */
228 val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
229 pci_write_config_dword(bdf, PCI_COMMAND, val32);
232 pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40);
235 pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI,
236 PCI_CFG_PIIX4_IDETIM_IDE);
237 pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
238 PCI_CFG_PIIX4_IDETIM_IDE);