3 * Corscience GmbH & Co.KG, Andreas Bießmann <biessmann@corscience.de>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/sdram.h>
11 #include <asm/arch/clk.h>
12 #include <asm/arch/hmatrix.h>
13 #include <asm/arch/mmu.h>
14 #include <asm/arch/portmux.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
21 .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
22 .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
23 .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
26 .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
27 .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
28 .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
29 | MMU_VMR_CACHE_WRBACK,
33 static const struct sdram_config sdram_config = {
34 /* Dual MT48LC16M16A2-7E (or equal) */
35 .data_bits = SDRAM_DATA_32BIT,
47 .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
50 int board_early_init_f(void)
52 /* Enable SDRAM in the EBI mux */
53 hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
55 portmux_enable_ebi(SDRAM_DATA_32BIT, 23, 0, PORTMUX_DRIVE_HIGH);
56 sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
58 portmux_enable_usart0(PORTMUX_DRIVE_MIN);
59 portmux_enable_usart1(PORTMUX_DRIVE_MIN);
60 #if defined(CONFIG_MACB)
61 /* set PHY reset and pwrdown to low */
62 portmux_select_gpio(PORTMUX_PORT_B, (1 << 29) | (1 << 30),
63 PORTMUX_DIR_OUTPUT | PORTMUX_INIT_LOW);
65 /* release PHYs reset */
66 gpio_set_value(GPIO_PIN_PB(29), 1);
68 portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
74 int board_early_init_r(void)
76 gd->bd->bi_phy_id[0] = 0x00;
81 int board_eth_init(bd_t *bi)
83 macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
87 /* vim: set noet ts=8: */