2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #if defined(CONFIG_MPC5200_DDR)
35 #include "mt46v16m16-75.h"
37 #include "mt48lc16m16a2-75.h"
41 static void sdram_start (int hi_addr)
43 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
45 /* unlock mode register */
46 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
47 __asm__ volatile ("sync");
49 /* precharge all banks */
50 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
51 __asm__ volatile ("sync");
54 /* set mode register: extended mode */
55 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
56 __asm__ volatile ("sync");
58 /* set mode register: reset DLL */
59 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
60 __asm__ volatile ("sync");
63 /* precharge all banks */
64 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
65 __asm__ volatile ("sync");
68 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
69 __asm__ volatile ("sync");
71 /* set mode register */
72 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
73 __asm__ volatile ("sync");
75 /* normal operation */
76 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
77 __asm__ volatile ("sync");
82 * ATTENTION: Although partially referenced initdram does NOT make real use
83 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
84 * is something else than 0x00000000.
87 long int initdram (int board_type)
93 /* setup SDRAM chip selects */
94 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
95 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
96 __asm__ volatile ("sync");
98 /* setup config registers */
99 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
100 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
101 __asm__ volatile ("sync");
105 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
106 __asm__ volatile ("sync");
109 /* find RAM size using SDRAM CS0 only */
111 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
113 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
121 /* memory smaller than 1MB is impossible */
122 if (dramsize < (1 << 20)) {
126 /* set SDRAM CS0 size according to the amount of RAM found */
128 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
129 __builtin_ffs(dramsize >> 20) - 1;
131 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
134 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
135 #else /* CFG_RAMBOOT */
137 /* retrieve size of memory connected to SDRAM CS0 */
138 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
139 if (dramsize >= 0x13) {
140 dramsize = (1 << (dramsize - 0x13)) << 20;
145 /* retrieve size of memory connected to SDRAM CS1 */
146 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
147 if (dramsize2 >= 0x13) {
148 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
153 #endif /* CFG_RAMBOOT */
155 /* return dramsize + dramsize2; */
159 int checkboard (void)
161 puts ("Board: INKA 4X0\n");
165 void flash_preinit(void)
168 * Now, when we are in RAM, enable flash write
169 * access for detection process.
170 * Note that CS_BOOT cannot be cleared when
171 * executing in flash.
173 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
176 #define GPIO_WKUP_7 0x80000000UL
177 #define GPIO_PSC3_9 0x04000000UL
179 int misc_init_f (void)
184 i = getenv_r("brightness", tmp, sizeof(tmp));
186 ? (int) simple_strtoul (tmp, NULL, 10)
191 /* Initialize GPIO output pins.
193 /* Configure GPT as GPIO output (and set them as they control low-active LEDs */
194 *(vu_long *)MPC5XXX_GPT0_ENABLE =
195 *(vu_long *)MPC5XXX_GPT1_ENABLE =
196 *(vu_long *)MPC5XXX_GPT2_ENABLE =
197 *(vu_long *)MPC5XXX_GPT3_ENABLE =
198 *(vu_long *)MPC5XXX_GPT4_ENABLE =
199 *(vu_long *)MPC5XXX_GPT5_ENABLE = 0x34;
201 /* Configure GPT7 as PWM timer, 1kHz, no ints. */
202 *(vu_long *)MPC5XXX_GPT7_ENABLE = 0;/* Disable */
203 *(vu_long *)MPC5XXX_GPT7_COUNTER = 0x020000fe;
204 *(vu_long *)MPC5XXX_GPT7_PWMCFG = (br << 16);
205 *(vu_long *)MPC5XXX_GPT7_ENABLE = 0x3;/* Enable PWM mode and start */
207 /* Configure PSC3_6,7 as GPIO output */
208 *(vu_long *)MPC5XXX_GPIO_ENABLE |= 0x00003000;
209 *(vu_long *)MPC5XXX_GPIO_DIR |= 0x00003000;
211 /* Configure PSC3_8 as GPIO output, no interrupt */
212 *(vu_long *)MPC5XXX_GPIO_SI_ENABLE |= 0x04000000;
213 *(vu_long *)MPC5XXX_GPIO_SI_DIR |= 0x04000000;
214 *(vu_long *)MPC5XXX_GPIO_SI_IEN &= ~0x04000000;
216 /* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
217 *(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= 0xc4000000;
218 *(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000;
220 /* Set LR mirror bit because it is low-active */
221 *(vu_long *)MPC5XXX_WU_GPIO_DATA |= GPIO_WKUP_7;
223 * Reset Coral-P graphics controller
225 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
226 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
227 *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC3_9;
232 static struct pci_controller hose;
234 extern void pci_mpc5xxx_init(struct pci_controller *);
236 void pci_init_board(void)
238 pci_mpc5xxx_init(&hose);
242 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
244 #define GPIO_PSC1_4 0x01000000UL
246 void init_ide_reset (void)
248 debug ("init_ide_reset\n");
250 /* Configure PSC1_4 as GPIO output for ATA reset */
251 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
252 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
254 *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
257 void ide_set_reset (int idereset)
259 debug ("ide_reset(%d)\n", idereset);
262 *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
263 /* Make a delay. MPC5200 spec says 25 usec min */
266 *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
269 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */