2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #if defined(CONFIG_MPC5200_DDR)
35 #include "mt46v16m16-75.h"
37 #include "mt48lc16m16a2-75.h"
41 static void sdram_start (int hi_addr)
43 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
45 /* unlock mode register */
46 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
48 __asm__ volatile ("sync");
50 /* precharge all banks */
51 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
53 __asm__ volatile ("sync");
56 /* set mode register: extended mode */
57 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
58 __asm__ volatile ("sync");
60 /* set mode register: reset DLL */
61 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
62 __asm__ volatile ("sync");
65 /* precharge all banks */
66 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
68 __asm__ volatile ("sync");
71 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
73 __asm__ volatile ("sync");
75 /* set mode register */
76 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
77 __asm__ volatile ("sync");
79 /* normal operation */
80 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
81 __asm__ volatile ("sync");
86 * ATTENTION: Although partially referenced initdram does NOT make real use
87 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
88 * is something else than 0x00000000.
91 long int initdram (int board_type)
97 /* setup SDRAM chip selects */
98 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
99 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
100 __asm__ volatile ("sync");
102 /* setup config registers */
103 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
104 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
105 __asm__ volatile ("sync");
109 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
110 __asm__ volatile ("sync");
113 /* find RAM size using SDRAM CS0 only */
115 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
117 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
125 /* memory smaller than 1MB is impossible */
126 if (dramsize < (1 << 20)) {
130 /* set SDRAM CS0 size according to the amount of RAM found */
132 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
133 __builtin_ffs(dramsize >> 20) - 1;
135 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
138 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
139 #else /* CFG_RAMBOOT */
141 /* retrieve size of memory connected to SDRAM CS0 */
142 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
143 if (dramsize >= 0x13) {
144 dramsize = (1 << (dramsize - 0x13)) << 20;
149 /* retrieve size of memory connected to SDRAM CS1 */
150 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
151 if (dramsize2 >= 0x13) {
152 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
157 #endif /* CFG_RAMBOOT */
159 /* return dramsize + dramsize2; */
163 int checkboard (void)
165 puts ("Board: INKA 4X0\n");
169 void flash_preinit(void)
172 * Now, when we are in RAM, enable flash write
173 * access for detection process.
174 * Note that CS_BOOT cannot be cleared when
175 * executing in flash.
177 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
180 #define GPIO_PSC3_9 0x04000000UL
182 int misc_init_f (void)
185 * Reset Coral-P graphics controller
187 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
188 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
189 *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC3_9;
194 static struct pci_controller hose;
196 extern void pci_mpc5xxx_init(struct pci_controller *);
198 void pci_init_board(void)
200 pci_mpc5xxx_init(&hose);
204 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
206 #define GPIO_PSC1_4 0x01000000UL
208 void init_ide_reset (void)
210 debug ("init_ide_reset\n");
212 /* Configure PSC1_4 as GPIO output for ATA reset */
213 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
214 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
216 *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
219 void ide_set_reset (int idereset)
221 debug ("ide_reset(%d)\n", idereset);
224 *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
225 /* Make a delay. MPC5200 spec says 25 usec min */
228 *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
231 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */