3 * ISEE 2007 SL, <www.iseebcn.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/mem.h>
29 #include <asm/arch/mmc_host_def.h>
30 #include <asm/arch/mux.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/arch/omap_gpmc.h>
33 #include <asm/mach-types.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 /* GPMC definitions for LAN9221 chips */
39 static const u32 gpmc_lan_config[] = {
40 NET_LAN9221_GPMC_CONFIG1,
41 NET_LAN9221_GPMC_CONFIG2,
42 NET_LAN9221_GPMC_CONFIG3,
43 NET_LAN9221_GPMC_CONFIG4,
44 NET_LAN9221_GPMC_CONFIG5,
45 NET_LAN9221_GPMC_CONFIG6,
50 * Description: Early hardware init.
54 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
56 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
61 #ifdef CONFIG_SPL_BUILD
63 * Routine: omap_rev_string
64 * Description: For SPL builds output board rev
66 void omap_rev_string(void)
71 * Routine: get_board_mem_timings
72 * Description: If we use SPL then there is no x-loader nor config header
73 * so we have to setup the DDR timings ourself on both banks.
75 void get_board_mem_timings(struct board_sdrc_timings *timings)
77 timings->mr = MICRON_V_MR_165;
78 #ifdef CONFIG_BOOT_NAND
79 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
80 timings->ctrla = MICRON_V_ACTIMA_200;
81 timings->ctrlb = MICRON_V_ACTIMB_200;
82 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
84 if (get_cpu_family() == CPU_OMAP34XX) {
85 timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
86 timings->ctrla = NUMONYX_V_ACTIMA_165;
87 timings->ctrlb = NUMONYX_V_ACTIMB_165;
88 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
91 timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
92 timings->ctrla = NUMONYX_V_ACTIMA_200;
93 timings->ctrlb = NUMONYX_V_ACTIMB_200;
94 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
101 * Routine: setup_net_chip
102 * Description: Setting up the configuration GPMC registers specific to the
105 #if defined(CONFIG_CMD_NET)
106 static void setup_net_chip(void)
108 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
110 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
113 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
114 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
115 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
116 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
117 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
118 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
119 &ctrl_base->gpmc_nadv_ale);
121 /* Make GPIO 64 as output pin and send a magic pulse through it */
122 if (!gpio_request(64, "")) {
123 gpio_direction_output(64, 0);
124 gpio_set_value(64, 1);
126 gpio_set_value(64, 0);
128 gpio_set_value(64, 1);
133 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
134 int board_mmc_init(bd_t *bis)
136 omap_mmc_init(0, 0, 0);
142 * Routine: misc_init_r
143 * Description: Configure board specific parts
145 int misc_init_r(void)
147 twl4030_power_init();
149 #if defined(CONFIG_CMD_NET)
159 * Routine: set_muxconf_regs
160 * Description: Setting up the configuration Mux registers specific to the
161 * hardware. Many pins need to be moved from protect to primary
164 void set_muxconf_regs(void)
169 int board_eth_init(bd_t *bis)
172 #ifdef CONFIG_SMC911X
173 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);