2 * Board functions for IGEP COM AQUILA/CYGNUS based boards
4 * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
14 * GNU General Public License for more details.
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/hardware.h>
22 #include <asm/arch/omap.h>
23 #include <asm/arch/ddr_defs.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/arch/mmc_host_def.h>
27 #include <asm/arch/sys_proto.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
40 /* MII mode defines */
41 #define RMII_MODE_ENABLE 0x4D
43 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
45 #ifdef CONFIG_SPL_BUILD
46 static const struct ddr_data ddr3_data = {
47 .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
48 .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
49 .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
50 .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
51 .datadldiff0 = PHY_DLL_LOCK_DIFF,
54 static const struct cmd_control ddr3_cmd_ctrl_data = {
55 .cmd0csratio = K4B2G1646EBIH9_RATIO,
56 .cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
57 .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
59 .cmd1csratio = K4B2G1646EBIH9_RATIO,
60 .cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
61 .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
63 .cmd2csratio = K4B2G1646EBIH9_RATIO,
64 .cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
65 .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
68 static struct emif_regs ddr3_emif_reg_data = {
69 .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
70 .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
71 .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
72 .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
73 .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
74 .zq_config = K4B2G1646EBIH9_ZQ_CFG,
75 .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
80 * Early system init of muxing and clocks.
85 * Save the boot parameters passed from romcode.
86 * We cannot delay the saving further than this,
87 * to prevent overwrites.
89 #ifdef CONFIG_SPL_BUILD
90 save_omap_boot_params();
93 /* WDT1 is already running when the bootloader gets control
94 * Disable it to avoid "random" resets
96 writel(0xAAAA, &wdtimer->wdtwspr);
97 while (readl(&wdtimer->wdtwwps) != 0x0)
99 writel(0x5555, &wdtimer->wdtwspr);
100 while (readl(&wdtimer->wdtwwps) != 0x0)
103 #ifdef CONFIG_SPL_BUILD
104 /* Setup the PLLs and the clocks for the peripherals */
107 /* Enable RTC32K clock */
110 enable_uart0_pin_mux();
115 preloader_console_init();
117 /* Configure board pin mux */
118 enable_board_pin_mux();
120 config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
121 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
126 * Basic board specific setup. Pinmux has been handled already.
130 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
137 #if defined(CONFIG_DRIVER_TI_CPSW)
138 static void cpsw_control(int enabled)
140 /* VTP can be added here */
145 static struct cpsw_slave_data cpsw_slaves[] = {
147 .slave_reg_ofs = 0x208,
148 .sliver_reg_ofs = 0xd80,
150 .phy_if = PHY_INTERFACE_MODE_RMII,
154 static struct cpsw_platform_data cpsw_data = {
155 .mdio_base = CPSW_MDIO_BASE,
156 .cpsw_base = CPSW_BASE,
159 .cpdma_reg_ofs = 0x800,
161 .slave_data = cpsw_slaves,
162 .ale_reg_ofs = 0xd00,
164 .host_port_reg_ofs = 0x108,
165 .hw_stats_reg_ofs = 0x900,
166 .mac_control = (1 << 5),
167 .control = cpsw_control,
169 .version = CPSW_CTRL_VERSION_2,
172 int board_eth_init(bd_t *bis)
176 uint32_t mac_hi, mac_lo;
178 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
179 /* try reading mac address from efuse */
180 mac_lo = readl(&cdev->macid0l);
181 mac_hi = readl(&cdev->macid0h);
182 mac_addr[0] = mac_hi & 0xFF;
183 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
184 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
185 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
186 mac_addr[4] = mac_lo & 0xFF;
187 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
188 if (is_valid_ether_addr(mac_addr))
189 eth_setenv_enetaddr("ethaddr", mac_addr);
192 writel(RMII_MODE_ENABLE, &cdev->miisel);
194 rv = cpsw_register(&cpsw_data);
196 printf("Error %d registering CPSW switch\n", rv);