3 * ISEE 2007 SL, <www.iseebcn.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <status_led.h>
16 #include <asm/arch/mem.h>
17 #include <asm/arch/mmc_host_def.h>
18 #include <asm/arch/mux.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/mach-types.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/mtd/nand.h>
23 #include <linux/mtd/nand.h>
24 #include <linux/mtd/onenand.h>
25 #include <jffs2/load_kernel.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 const omap3_sysinfo sysinfo = {
32 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
35 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
36 "IGEP COM MODULE/ELECTRON",
38 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
41 #if defined(CONFIG_ENV_IS_IN_ONENAND)
48 static const struct ns16550_platdata igep_serial = {
49 .base = OMAP34XX_UART3,
51 .clock = V_NS16550_CLK
54 U_BOOT_DEVICE(igep_uart) = {
61 * Description: Early hardware init.
67 /* find out flash memory type, assume NAND first */
68 gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
71 /* Issue a RESET and then READID */
72 writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
73 writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
74 while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
75 != NAND_STATUS_READY) {
78 gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
79 gpmc_init(); /* reinitialize for OneNAND */
85 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
87 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
88 status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
94 #ifdef CONFIG_SPL_BUILD
96 * Routine: get_board_mem_timings
97 * Description: If we use SPL then there is no x-loader nor config header
98 * so we have to setup the DDR timings ourself on both banks.
100 void get_board_mem_timings(struct board_sdrc_timings *timings)
102 int mfr, id, err = identify_nand_chip(&mfr, &id);
104 timings->mr = MICRON_V_MR_165;
105 if (!err && mfr == NAND_MFR_MICRON) {
106 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
107 timings->ctrla = MICRON_V_ACTIMA_200;
108 timings->ctrlb = MICRON_V_ACTIMB_200;
109 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
110 gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
112 if (get_cpu_family() == CPU_OMAP34XX) {
113 timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
114 timings->ctrla = NUMONYX_V_ACTIMA_165;
115 timings->ctrlb = NUMONYX_V_ACTIMB_165;
116 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
118 timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
119 timings->ctrla = NUMONYX_V_ACTIMA_200;
120 timings->ctrlb = NUMONYX_V_ACTIMB_200;
121 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
123 gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
127 #ifdef CONFIG_SPL_OS_BOOT
128 int spl_start_uboot(void)
130 /* break into full u-boot on 'c' */
131 if (serial_tstc() && serial_getc() == 'c')
139 int onenand_board_init(struct mtd_info *mtd)
141 if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
142 struct onenand_chip *this = mtd->priv;
143 this->base = (void *)CONFIG_SYS_ONENAND_BASE;
149 #if defined(CONFIG_CMD_NET)
150 static void reset_net_chip(int gpio)
152 if (!gpio_request(gpio, "eth nrst")) {
153 gpio_direction_output(gpio, 1);
155 gpio_set_value(gpio, 0);
157 gpio_set_value(gpio, 1);
163 * Routine: setup_net_chip
164 * Description: Setting up the configuration GPMC registers specific to the
167 static void setup_net_chip(void)
169 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
170 static const u32 gpmc_lan_config[] = {
171 NET_LAN9221_GPMC_CONFIG1,
172 NET_LAN9221_GPMC_CONFIG2,
173 NET_LAN9221_GPMC_CONFIG3,
174 NET_LAN9221_GPMC_CONFIG4,
175 NET_LAN9221_GPMC_CONFIG5,
176 NET_LAN9221_GPMC_CONFIG6,
179 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
180 CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
182 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
183 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
184 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
185 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
186 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
187 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
188 &ctrl_base->gpmc_nadv_ale);
193 int board_eth_init(bd_t *bis)
195 #ifdef CONFIG_SMC911X
196 return smc911x_initialize(0, CONFIG_SMC911X_BASE);
202 static inline void setup_net_chip(void) {}
205 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
206 int board_mmc_init(bd_t *bis)
208 return omap_mmc_init(0, 0, 0, -1, -1);
212 #if defined(CONFIG_GENERIC_MMC)
213 void board_mmc_power_init(void)
215 twl4030_power_mmc_init(0);
221 switch (gd->bd->bi_arch_number) {
222 case MACH_TYPE_IGEP0020:
223 setenv("fdtfile", "omap3-igep0020.dtb");
225 case MACH_TYPE_IGEP0030:
226 setenv("fdtfile", "omap3-igep0030.dtb");
232 * Routine: misc_init_r
233 * Description: Configure board specific parts
235 int misc_init_r(void)
237 twl4030_power_init();
241 omap_die_id_display();
248 void board_mtdparts_default(const char **mtdids, const char **mtdparts)
250 struct mtd_info *mtd = get_mtd_device(NULL, 0);
253 static char parts[48];
254 const char *linux_name = "omap2-nand";
255 if (strncmp(mtd->name, "onenand0", 8) == 0)
256 linux_name = "omap2-onenand";
257 snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name);
258 snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)",
259 linux_name, 4 * mtd->erasesize >> 10);
266 * Routine: set_muxconf_regs
267 * Description: Setting up the configuration Mux registers specific to the
268 * hardware. Many pins need to be moved from protect to primary
271 void set_muxconf_regs(void)
275 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
279 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)