2 * SPDX-License-Identifier: GPL-2.0+
5 #include <asm/arch/mem.h>
6 #include <asm/arch/sys_proto.h>
7 #include <jffs2/load_kernel.h>
8 #include <linux/mtd/rawnand.h>
12 * Routine: get_board_mem_timings
13 * Description: If we use SPL then there is no x-loader nor config header
14 * so we have to setup the DDR timings ourself on both banks.
16 void get_board_mem_timings(struct board_sdrc_timings *timings)
18 int mfr, id, err = identify_nand_chip(&mfr, &id);
20 timings->mr = MICRON_V_MR_165;
24 timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
25 timings->ctrla = HYNIX_V_ACTIMA_200;
26 timings->ctrlb = HYNIX_V_ACTIMB_200;
29 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
30 timings->ctrla = MICRON_V_ACTIMA_200;
31 timings->ctrlb = MICRON_V_ACTIMB_200;
34 /* Should not happen... */
37 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
38 gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
40 if (get_cpu_family() == CPU_OMAP34XX) {
41 timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
42 timings->ctrla = NUMONYX_V_ACTIMA_165;
43 timings->ctrlb = NUMONYX_V_ACTIMB_165;
44 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
46 timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
47 timings->ctrla = NUMONYX_V_ACTIMA_200;
48 timings->ctrlb = NUMONYX_V_ACTIMB_200;
49 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
51 gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
55 #ifdef CONFIG_SPL_OS_BOOT
56 int spl_start_uboot(void)
58 /* break into full u-boot on 'c' */
59 if (serial_tstc() && serial_getc() == 'c')