2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
6 * SPDX-License-Identifier: GPL-2.0+
13 #ifdef CONFIG_STATUS_LED
14 # include <status_led.h>
17 /* ------------------------------------------------------------------------- */
19 static long int dram_size (long int, long int *, long int);
21 /* ------------------------------------------------------------------------- */
23 #define _NOT_USED_ 0xFFFFFFFF
26 * 50 MHz SHARC access using UPM A
28 const uint sharc_table[] = {
30 * Single Read. (Offset 0 in UPM RAM)
32 0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
33 0xFFFFEC05, /* last */
34 _NOT_USED_, _NOT_USED_, _NOT_USED_,
36 * Burst Read. (Offset 8 in UPM RAM)
39 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
40 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
41 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
42 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
44 * Single Write. (Offset 18 in UPM RAM)
46 0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
47 0xFFFFEC05, /* last */
48 _NOT_USED_, _NOT_USED_, _NOT_USED_,
50 * Burst Write. (Offset 20 in UPM RAM)
53 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
54 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
55 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
56 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
58 * Refresh (Offset 30 in UPM RAM)
61 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
62 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
63 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
65 * Exception. (Offset 3c in UPM RAM)
67 0x7FFFFC07, /* last */
68 _NOT_USED_, _NOT_USED_, _NOT_USED_,
73 * 50 MHz SDRAM access using UPM B
75 const uint sdram_table[] = {
77 * Single Read. (Offset 0 in UPM RAM)
79 0x0E26FC04, 0x11ADFC04, 0xEFBBBC00, 0x1FF77C45, /* last */
82 * SDRAM Initialization (offset 5 in UPM RAM)
84 * This is no UPM entry point. The following definition uses
85 * the remaining space to establish an initialization
86 * sequence, which is executed by a RUN command.
89 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
91 * Burst Read. (Offset 8 in UPM RAM)
93 0x0E26FC04, 0x10ADFC04, 0xF0AFFC00, 0xF0AFFC00,
94 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C45, /* last */
96 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
97 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
99 * Single Write. (Offset 18 in UPM RAM)
101 0x1F27FC04, 0xEEAEBC04, 0x01B93C00, 0x1FF77C45, /* last */
102 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
104 * Burst Write. (Offset 20 in UPM RAM)
106 0x0E26BC00, 0x10AD7C00, 0xF0AFFC00, 0xF0AFFC00,
107 0xE1BBBC04, 0x1FF77C45, /* last */
108 _NOT_USED_, _NOT_USED_,
109 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
110 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
112 * Refresh (Offset 30 in UPM RAM)
114 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC84,
115 0xFFFFFC05, /* last */
116 _NOT_USED_, _NOT_USED_, _NOT_USED_,
117 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
119 * Exception. (Offset 3c in UPM RAM)
121 0x7FFFFC07, /* last */
122 _NOT_USED_, _NOT_USED_, _NOT_USED_,
125 /* ------------------------------------------------------------------------- */
129 * Check Board Identity:
133 int checkboard (void)
136 puts ("Board: IVMS8\n");
139 puts ("Board: IVM-L8/24\n");
144 /* ------------------------------------------------------------------------- */
146 phys_size_t initdram (int board_type)
148 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
149 volatile memctl8xx_t *memctl = &immr->im_memctl;
152 /* enable SDRAM clock ("switch on" SDRAM) */
153 immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_SDRAM_CLKE); /* GPIO */
154 immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_SDRAM_CLKE); /* active output */
155 immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_SDRAM_CLKE; /* output */
156 immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_SDRAM_CLKE; /* assert SDRAM CLKE */
160 * Map controller bank 1 for ELIC SACCO
162 memctl->memc_or1 = CONFIG_SYS_OR1;
163 memctl->memc_br1 = CONFIG_SYS_BR1;
166 * Map controller bank 2 for ELIC EPIC
168 memctl->memc_or2 = CONFIG_SYS_OR2;
169 memctl->memc_br2 = CONFIG_SYS_BR2;
172 * Configure UPMA for SHARC
174 upmconfig (UPMA, (uint *) sharc_table,
175 sizeof (sharc_table) / sizeof (uint));
177 #if defined(CONFIG_IVML24)
179 * Map controller bank 4 for HDLC Address space
181 memctl->memc_or4 = CONFIG_SYS_OR4;
182 memctl->memc_br4 = CONFIG_SYS_BR4;
186 * Map controller bank 5 for SHARC
188 memctl->memc_or5 = CONFIG_SYS_OR5;
189 memctl->memc_br5 = CONFIG_SYS_BR5;
191 memctl->memc_mamr = 0x00001000;
194 * Configure UPMB for SDRAM
196 upmconfig (UPMB, (uint *) sdram_table,
197 sizeof (sdram_table) / sizeof (uint));
199 memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
201 memctl->memc_mar = 0x00000088;
204 * Map controller bank 3 to the SDRAM bank at preliminary address.
206 memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
207 memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
209 memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */
212 memctl->memc_mcr = 0x80806105; /* precharge */
214 memctl->memc_mcr = 0x80806106; /* load mode register */
216 memctl->memc_mcr = 0x80806130; /* autorefresh */
218 memctl->memc_mcr = 0x80806130; /* autorefresh */
220 memctl->memc_mcr = 0x80806130; /* autorefresh */
222 memctl->memc_mcr = 0x80806130; /* autorefresh */
224 memctl->memc_mcr = 0x80806130; /* autorefresh */
226 memctl->memc_mcr = 0x80806130; /* autorefresh */
228 memctl->memc_mcr = 0x80806130; /* autorefresh */
230 memctl->memc_mcr = 0x80806130; /* autorefresh */
232 memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
235 * Check Bank 0 Memory Size for re-configuration
238 dram_size (CONFIG_SYS_MBMR_8COL, (long *) SDRAM_BASE3_PRELIM,
241 memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE;
246 /* ------------------------------------------------------------------------- */
249 * Check memory range for valid RAM. A simple memory test determines
250 * the actually available RAM size between addresses `base' and
251 * `base + maxsize'. Some (not all) hardware errors are detected:
252 * - short between address lines
253 * - short between data lines
256 static long int dram_size (long int mamr_value, long int *base,
259 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
260 volatile memctl8xx_t *memctl = &immr->im_memctl;
262 memctl->memc_mbmr = mamr_value;
264 return (get_ram_size (base, maxsize));
267 /* ------------------------------------------------------------------------- */
269 void reset_phy (void)
271 immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
273 /* De-assert Ethernet Powerdown */
274 immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* GPIO */
275 immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* active output */
276 immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_ETH_POWERDOWN; /* output */
277 immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */
281 * RESET is implemented by a positive pulse of at least 1 us
284 * Configure RESET pins for NS DP83843 PHY, and RESET chip.
286 * Note: The RESET pin is high active, but there is an
287 * inverter on the SPD823TS board...
289 immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_ETH_RESET);
290 immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_ETH_RESET;
291 /* assert RESET signal of PHY */
292 immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_ETH_RESET);
294 /* de-assert RESET signal of PHY */
295 immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_ETH_RESET;
299 /* ------------------------------------------------------------------------- */
301 void show_boot_progress (int status)
303 #if defined(CONFIG_STATUS_LED)
304 # if defined(STATUS_LED_YELLOW)
305 status_led_set (STATUS_LED_YELLOW,
306 (status < 0) ? STATUS_LED_ON : STATUS_LED_OFF);
307 # endif /* STATUS_LED_YELLOW */
308 # if defined(STATUS_LED_BOOT)
309 if (status == BOOTSTAGE_ID_DECOMP_IMAGE)
310 status_led_set (STATUS_LED_BOOT, STATUS_LED_OFF);
311 # endif /* STATUS_LED_BOOT */
312 #endif /* CONFIG_STATUS_LED */
315 /* ------------------------------------------------------------------------- */
317 void ide_set_reset (int on)
319 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
323 * Configure PC for IDE Reset Pin
325 if (on) { /* assert RESET */
326 immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
328 #ifdef CONFIG_SYS_PB_12V_ENABLE
329 /* 12V Enable output OFF */
330 immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_12V_ENABLE);
332 immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_12V_ENABLE);
333 immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_12V_ENABLE);
334 immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_12V_ENABLE;
336 /* wait 500 ms for the voltage to stabilize */
337 for (i = 0; i < 500; ++i)
339 #endif /* CONFIG_SYS_PB_12V_ENABLE */
340 } else { /* release RESET */
341 #ifdef CONFIG_SYS_PB_12V_ENABLE
342 /* 12V Enable output ON */
343 immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_12V_ENABLE;
344 #endif /* CONFIG_SYS_PB_12V_ENABLE */
346 #ifdef CONFIG_SYS_PB_IDE_MOTOR
347 /* configure IDE Motor voltage monitor pin as input */
348 immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_IDE_MOTOR);
349 immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_IDE_MOTOR);
350 immr->im_cpm.cp_pbdir &= ~(CONFIG_SYS_PB_IDE_MOTOR);
352 /* wait up to 1 s for the motor voltage to stabilize */
353 for (i = 0; i < 1000; ++i) {
354 if ((immr->im_cpm.cp_pbdat
355 & CONFIG_SYS_PB_IDE_MOTOR) != 0)
360 if (i == 1000) { /* Timeout */
361 printf("\nWarning: 5V for IDE Motor missing\n");
362 #ifdef CONFIG_STATUS_LED
363 #ifdef STATUS_LED_YELLOW
364 status_led_set(STATUS_LED_YELLOW, STATUS_LED_ON);
366 #ifdef STATUS_LED_GREEN
367 status_led_set(STATUS_LED_GREEN, STATUS_LED_OFF);
369 #endif /* CONFIG_STATUS_LED */
371 #endif /* CONFIG_SYS_PB_IDE_MOTOR */
373 immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET;
376 /* program port pin as GPIO output */
377 immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET);
378 immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET);
379 immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET;
382 /* ------------------------------------------------------------------------- */