2 * Copyright (c) 2004 Picture Elements, Inc.
3 * Stephen Williams (steve@icarus.com)
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/ppc4xx.h>
10 #include <asm/processor.h>
12 # define SDRAM_LEN 0x08000000
15 * this is even after checkboard. It returns the size of the SDRAM
16 * that we have installed. This function is called by board_init_f
17 * in arch/powerpc/lib/board.c to initialize the memory and return what I
20 phys_size_t initdram (int board_type)
22 /* Configure the SDRAMS */
24 /* disable memory controller */
25 mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
26 mtdcr (SDRAM0_CFGDATA, 0x00000000);
30 /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
31 mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR0);
32 mtdcr (SDRAM0_CFGDATA, 0xffffffff);
34 /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
35 mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR1);
36 mtdcr (SDRAM0_CFGDATA, 0xffffffff);
38 /* Clear SDRAM0_ECCCFG (disable ECC) */
39 mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
40 mtdcr (SDRAM0_CFGDATA, 0x00000000);
42 /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
43 mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCESR);
44 mtdcr (SDRAM0_CFGDATA, 0xffffffff);
46 /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */
47 mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
48 mtdcr (SDRAM0_CFGDATA, 0x010a4016);
50 /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */
51 mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
52 mtdcr (SDRAM0_CFGDATA, 0x00084001);
54 /* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */
55 mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
56 mtdcr (SDRAM0_CFGDATA, 0x04084001);
58 /* Memory Bank 2 Config == BE=0 */
59 mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
60 mtdcr (SDRAM0_CFGDATA, 0x00000000);
62 /* Memory Bank 3 Config == BE=0 */
63 mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
64 mtdcr (SDRAM0_CFGDATA, 0x00000000);
66 /* refresh timer = 0x400 */
67 mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
68 mtdcr (SDRAM0_CFGDATA, 0x04000000);
70 /* Power management idle timer set to the default. */
71 mtdcr (SDRAM0_CFGADDR, SDRAM0_PMIT);
72 mtdcr (SDRAM0_CFGDATA, 0x07c00000);
76 /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */
77 mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
78 mtdcr (SDRAM0_CFGDATA, 0x80e00000);
84 * The U-Boot core, as part of the initialization to prepare for
85 * loading the monitor into SDRAM, requests of this function that the
86 * memory be tested. Return 0 if the memory tests OK.
93 volatile unsigned long *sdram;
96 printf ("SDRAM Controller Registers --\n");
98 mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
99 val = mfdcr (SDRAM0_CFGDATA);
100 printf (" SDRAM0_CFG : 0x%08x\n", val);
102 mtdcr (SDRAM0_CFGADDR, 0x24);
103 val = mfdcr (SDRAM0_CFGDATA);
104 printf (" SDRAM0_STATUS: 0x%08x\n", val);
106 mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
107 val = mfdcr (SDRAM0_CFGDATA);
108 printf (" SDRAM0_B0CR : 0x%08x\n", val);
110 mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
111 val = mfdcr (SDRAM0_CFGDATA);
112 printf (" SDRAM0_B1CR : 0x%08x\n", val);
114 mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
115 val = mfdcr (SDRAM0_CFGDATA);
116 printf (" SDRAM0_TR : 0x%08x\n", val);
118 mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
119 val = mfdcr (SDRAM0_CFGDATA);
120 printf (" SDRAM0_RTR : 0x%08x\n", val);
123 /* Wait for memory to be ready by testing MRSCMPbit
124 bit. Really, there should already have been plenty of time,
125 given it was started long ago. But, best to check. */
126 for (idx = 0; idx < 1000000; idx += 1) {
127 mtdcr (SDRAM0_CFGADDR, 0x24);
128 val = mfdcr (SDRAM0_CFGDATA);
129 if (val & 0x80000000)
133 if (!(val & 0x80000000)) {
134 printf ("SDRAM ERROR: SDRAM0_STATUS never set!\n");
138 /* Start memory test. */
139 printf ("test: %u MB - ", SDRAM_LEN / 1048576);
141 sdram = (unsigned long *) CONFIG_SYS_SDRAM_BASE;
144 for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) {
145 sdram[idx + 0] = idx;
146 sdram[idx + 1] = ~idx;
151 for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) {
152 if (sdram[idx + 0] != idx)
154 if (sdram[idx + 1] != ~idx)
162 printf ("FIRST ERROR at %p: 0x%08lx:0x%08lx != 0x%08lx:0x%08lx\n",
163 sdram + idx, sdram[idx + 0], sdram[idx + 1], idx, ~idx);