2 * Copyright (C) 2012 Marek Vasut <marex@denx.de>
3 * on behalf of DENX Software Engineering GmbH
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/cpu.h>
11 #include <asm/arch/kirkwood.h>
12 #include <asm/arch/mpp.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 #define TK71_OE_LOW (~0)
18 #define TK71_OE_HIGH (~0)
19 #define TK71_OE_VAL_LOW (0)
20 #define TK71_OE_VAL_HIGH (0)
22 int board_early_init_f(void)
25 * default gpio configuration
26 * There are maximum 64 gpios controlled through 2 sets of registers
27 * the below configuration configures mainly initial LED status
29 kw_config_gpio(TK71_OE_VAL_LOW,
31 TK71_OE_LOW, TK71_OE_HIGH);
33 /* Multi-Purpose Pins Functionality configuration */
34 static const u32 kwmpp_config[] = {
87 kirkwood_mpp_conf(kwmpp_config, NULL);
95 * arch number of board
97 gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
99 /* adress of boot parameters */
100 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
105 #ifdef CONFIG_CMD_NET
107 #define MV88E1116_MAC_CTRL2_REG 21
108 #define MV88E1116_PGADR_REG 22
109 #define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
110 #define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
112 static void mv_phy_88e1118_init(char *name)
117 if (miiphy_set_current_dev(name))
120 /* command to read PHY dev address */
121 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
122 printf("Err..%s could not read PHY dev address\n",
128 * Enable RGMII delay on Tx and Rx for CPU port
129 * Ref: sec 4.7.2 of chip datasheet
131 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
132 miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®);
133 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
134 miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
135 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
138 miiphy_reset(name, devadr);
140 printf("88E1118 Initialized on %s\n", name);
143 /* Configure and enable Switch and PHY */
146 /* configure and initialize PHY */
147 mv_phy_88e1118_init("egiga0");