2 * Copyright (C) 2012 Marek Vasut <marex@denx.de>
3 * on behalf of DENX Software Engineering GmbH
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
26 #include <asm/arch/cpu.h>
27 #include <asm/arch/kirkwood.h>
28 #include <asm/arch/mpp.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 #define TK71_OE_LOW (~0)
34 #define TK71_OE_HIGH (~0)
35 #define TK71_OE_VAL_LOW (0)
36 #define TK71_OE_VAL_HIGH (0)
38 int board_early_init_f(void)
41 * default gpio configuration
42 * There are maximum 64 gpios controlled through 2 sets of registers
43 * the below configuration configures mainly initial LED status
45 kw_config_gpio(TK71_OE_VAL_LOW,
47 TK71_OE_LOW, TK71_OE_HIGH);
49 /* Multi-Purpose Pins Functionality configuration */
50 u32 kwmpp_config[] = {
103 kirkwood_mpp_conf(kwmpp_config, NULL);
111 * arch number of board
113 gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
115 /* adress of boot parameters */
116 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
121 #ifdef CONFIG_CMD_NET
123 #define MV88E1116_MAC_CTRL2_REG 21
124 #define MV88E1116_PGADR_REG 22
125 #define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
126 #define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
128 static void mv_phy_88e1118_init(char *name)
133 if (miiphy_set_current_dev(name))
136 /* command to read PHY dev address */
137 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
138 printf("Err..%s could not read PHY dev address\n",
144 * Enable RGMII delay on Tx and Rx for CPU port
145 * Ref: sec 4.7.2 of chip datasheet
147 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
148 miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®);
149 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
150 miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
151 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
154 miiphy_reset(name, devadr);
156 printf("88E1118 Initialized on %s\n", name);
159 /* Configure and enable Switch and PHY */
162 /* configure and initialize PHY */
163 mv_phy_88e1118_init("egiga0");