2 * (C) Copyright 2009 DENX Software Engineering
3 * Author: John Rigby <jrigby@gmail.com>
5 * Based on U-Boot and RedBoot sources for several different i.mx
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/macro.h>
25 #include <asm/arch/macro.h>
31 * first enable CLKO debug output
32 * 0x40000000 enables the debug CLKO signal
33 * 0x05000000 sets CLKO divider to 6
34 * 0x00600000 makes CLKO parent clk the USB clk
36 write32 0x53f80064, 0x45600000
38 /* CCTL: ARM = 399 MHz, AHB = 133 MHz */
39 write32 0x53f80008, 0x20034000
42 * PCDR2: NFC = 33.25 MHz
43 * This is required for the NAND Flash of this board, which is a Samsung
44 * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with
45 * the NFC driver in symmetric (i.e. one-cycle) mode.
47 write32 0x53f80020, 0x01010103
50 * enable all implemented clocks in all three
51 * clock control registers
53 write32 0x53f8000c, 0x1fffffff
54 write32 0x53f80010, 0xffffffff
55 write32 0x53f80014, 0xfdfff
60 * ddr_type is 3.3v SDRAM
62 write32 0x43fac454, 0x800
66 * sdram controller init
68 .macro init_sdram_bank bankaddr, ctl, cfg
72 * reset SDRAM controller
73 * then wait for initialization to complete
77 1: ldr r3, [r0, #0x10]
82 str r1, [r0, #\cfg] /* config */
84 ldr r1, =0x92116480 /* control | precharge */
85 str r1, [r0, #\ctl] /* write command to controller */
86 str r1, [r2, #0x400] /* command encoded in address */
88 ldr r1, =0xa2116480 /* auto refresh */
90 ldrb r3, [r2] /* read dram twice to auto refresh */
93 ldr r1, =0xb2116480 /* control | load mode */
94 str r1, [r0, #\ctl] /* write command to controller */
95 strb r1, [r2, #0x33] /* command encoded in address */
97 ldr r1, =0x82116480 /* control | normal (0)*/
98 str r1, [r0, #\ctl] /* write command to controller */
108 init_sdram_bank 0x80000000, 0x0, 0x4
110 init_sdram_bank 0x90000000, 0x8, 0xc