3 * Marvell Semiconductor <www.marvell.com>
4 * Prafulla Wadaskar <prafulla@marvell.com>
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
10 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
38 #include <asm/arch/cpu.h>
39 #include <asm/arch/kirkwood.h>
40 #include <asm/arch/mpp.h>
42 #include "../common/common.h"
44 DECLARE_GLOBAL_DATA_PTR;
47 * BOCO FPGA definitions
50 #define REG_CTRL_H 0x02
51 #define MASK_WRL_UNITRUN 0x01
52 #define MASK_RBX_PGY_PRESENT 0x40
53 #define REG_IRQ_CIRQ2 0x2d
54 #define MASK_RBI_DEFECT_16 0x01
56 /* Multi-Purpose Pins Functionality configuration */
57 u32 kwmpp_config[] = {
66 #if defined(CONFIG_SOFT_I2C)
70 #if defined(CONFIG_HARD_I2C)
76 MPP12_GPO, /* Reserved */
79 MPP15_GPIO, /* Not used */
80 MPP16_GPIO, /* Not used */
81 MPP17_GPIO, /* Reserved */
98 MPP34_GPIO, /* CDL1 (input) */
99 MPP35_GPIO, /* CDL2 (input) */
100 MPP36_GPIO, /* MAIN_IRQ (input) */
101 MPP37_GPIO, /* BOARD_LED */
102 MPP38_GPIO, /* Piggy3 LED[1] */
103 MPP39_GPIO, /* Piggy3 LED[2] */
104 MPP40_GPIO, /* Piggy3 LED[3] */
105 MPP41_GPIO, /* Piggy3 LED[4] */
106 MPP42_GPIO, /* Piggy3 LED[5] */
107 MPP43_GPIO, /* Piggy3 LED[6] */
108 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */
109 MPP45_GPIO, /* Piggy3 LED[8] */
110 MPP46_GPIO, /* Reserved */
111 MPP47_GPIO, /* Reserved */
112 MPP48_GPIO, /* Reserved */
113 MPP49_GPIO, /* SW_INTOUTn */
117 #if defined(CONFIG_KM_MGCOGE3UN)
119 * Wait for startup OK from mgcoge3ne
121 int startup_allowed(void)
126 * Read CIRQ16 bit (bit 0)
128 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
129 printf("%s: Error reading Boco\n", __func__);
131 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
137 #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
139 * All boards with PIGGY4 connected via a simple switch have ethernet always
142 int ethernet_present(void)
147 int ethernet_present(void)
152 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
153 printf("%s: Error reading Boco\n", __func__);
156 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
163 int initialize_unit_leds(void)
166 * Init the unit LEDs per default they all are
167 * ok apart from bootstat
171 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
172 printf("%s: Error reading Boco\n", __func__);
175 buf |= MASK_WRL_UNITRUN;
176 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
177 printf("%s: Error writing Boco\n", __func__);
183 #if defined(CONFIG_BOOTCOUNT_LIMIT)
184 void set_bootcount_addr(void)
187 unsigned int bootcountaddr;
188 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
189 sprintf((char *)buf, "0x%x", bootcountaddr);
190 setenv("bootcountaddr", (char *)buf);
194 int misc_init_r(void)
199 str = getenv("mach_type");
201 mach_type = simple_strtoul(str, NULL, 10);
202 printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
203 gd->bd->bi_arch_number = mach_type;
205 #if defined(CONFIG_KM_MGCOGE3UN)
207 wait_for_ne = getenv("waitforne");
208 if (wait_for_ne != NULL) {
209 if (strcmp(wait_for_ne, "true") == 0) {
213 while (startup_allowed() == 0) {
215 (void) getc(); /* consume input */
222 puts("wait\b\b\b\b");
229 printf("\nAbort waiting for ne\n");
236 initialize_unit_leds();
238 #if defined(CONFIG_BOOTCOUNT_LIMIT)
239 set_bootcount_addr();
244 int board_early_init_f(void)
246 #if defined(CONFIG_SOFT_I2C)
249 /* set the 2 bitbang i2c pins as output gpios */
250 tmp = readl(KW_GPIO0_BASE + 4);
251 writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4);
253 /* adjust SDRAM size for bank 0 */
254 kw_sdram_size_adjust(0);
255 kirkwood_mpp_conf(kwmpp_config, NULL);
262 * arch number of board
264 gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;
266 /* address of boot parameters */
267 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
270 * The KM_FLASH_GPIO_PIN switches between using a
271 * NAND or a SPI FLASH. Set this pin on start
274 kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
275 kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
277 #if defined(CONFIG_SOFT_I2C)
279 * Reinit the GPIO for I2C Bitbang driver so that the now
280 * available gpio framework is consistent. The calls to
281 * direction output in are not necessary, they are already done in
284 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
285 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
288 #if defined(CONFIG_SYS_EEPROM_WREN)
289 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
290 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
293 #if defined(CONFIG_KM_FPGA_CONFIG)
294 trigger_fpga_config();
300 int board_late_init(void)
302 #if defined(CONFIG_KMCOGE5UN)
303 /* I/O pin to erase flash RGPP09 = MPP43 */
304 #define KM_FLASH_ERASE_ENABLE 43
305 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
307 /* if pin 1 do full erase */
308 if (dip_switch != 0) {
309 /* start bootloader */
310 puts("DIP: Enabled\n");
311 setenv("actual_bank", "0");
315 #if defined(CONFIG_KM_FPGA_CONFIG)
316 wait_for_fpga_config();
318 toggle_eeprom_spi_bus();
323 int board_spi_claim_bus(struct spi_slave *slave)
325 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
330 void board_spi_release_bus(struct spi_slave *slave)
332 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
335 #if (defined(CONFIG_KM_PIGGY4_88E6061))
337 #define PHY_LED_SEL_REG 0x18
338 #define PHY_LED0_LINK (0x5)
339 #define PHY_LED1_ACT (0x8<<4)
340 #define PHY_LED2_INT (0xe<<8)
341 #define PHY_SPEC_CTRL_REG 0x1c
342 #define PHY_RGMII_CLK_STABLE (0x1<<10)
343 #define PHY_CLSA (0x1<<1)
345 /* Configure and enable MV88E3018 PHY */
348 char *name = "egiga0";
351 if (miiphy_set_current_dev(name))
354 /* RGMII clk transition on data stable */
355 if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®))
356 printf("Error reading PHY spec ctrl reg\n");
357 if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
358 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
359 printf("Error writing PHY spec ctrl reg\n");
362 if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
363 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
364 printf("Error writing PHY LED reg\n");
367 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
369 #elif defined(CONFIG_KM_PIGGY4_88E6352)
371 #include <mv88e6352.h>
373 #if defined(CONFIG_KM_NUSA)
374 struct mv88e_sw_reg extsw_conf[] = {
376 * port 0, PIGGY4, autoneg
377 * first the fix for the 1000Mbits Autoneg, this is from
378 * a Marvell errata, the regs are undocumented
380 { PHY(0), PHY_PAGE, AN1000FIX_PAGE },
381 { PHY(0), PHY_STATUS, AN1000FIX },
382 { PHY(0), PHY_PAGE, 0 },
383 /* now the real port and phy configuration */
384 { PORT(0), PORT_PHY, NO_SPEED_FOR },
385 { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
386 { PHY(0), PHY_1000_CTRL, NO_ADV },
387 { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
388 { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
391 { PORT(1), PORT_CTRL, PORT_DIS },
392 { PHY(1), PHY_CTRL, PHY_PWR_DOWN },
393 { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
395 { PORT(2), PORT_CTRL, PORT_DIS },
396 { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
397 { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
399 { PORT(3), PORT_CTRL, PORT_DIS },
400 { PHY(3), PHY_CTRL, PHY_PWR_DOWN },
401 { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
402 /* port 4, ICNEV, SerDes, SGMII */
403 { PORT(4), PORT_STATUS, NO_PHY_DETECT },
404 { PORT(4), PORT_PHY, SPEED_1000_FOR },
405 { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
406 { PHY(4), PHY_CTRL, PHY_PWR_DOWN },
407 { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
408 /* port 5, CPU_RGMII */
409 { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
410 FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
411 FULL_DPX_FOR | SPEED_1000_FOR },
412 { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
413 /* port 6, unused, this port has no phy */
414 { PORT(6), PORT_CTRL, PORT_DIS },
417 struct mv88e_sw_reg extsw_conf[] = {};
422 #if defined(CONFIG_KM_MVEXTSW_ADDR)
423 char *name = "egiga0";
425 if (miiphy_set_current_dev(name))
428 mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
429 ARRAY_SIZE(extsw_conf));
430 mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
435 /* Configure and enable MV88E1118 PHY on the piggy*/
438 char *name = "egiga0";
440 if (miiphy_set_current_dev(name))
444 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
449 #if defined(CONFIG_HUSH_INIT_VAR)
450 int hush_init_var(void)
457 #if defined(CONFIG_SOFT_I2C)
458 void set_sda(int state)
464 void set_scl(int state)
477 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
481 #if defined(CONFIG_POST)
483 #define KM_POST_EN_L 44
484 #define POST_WORD_OFF 8
486 int post_hotkeys_pressed(void)
488 #if defined(CONFIG_KM_COGE5UN)
489 return kw_gpio_get_value(KM_POST_EN_L);
491 return !kw_gpio_get_value(KM_POST_EN_L);
495 ulong post_word_load(void)
497 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
498 return in_le32(addr);
501 void post_word_store(ulong value)
503 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
504 out_le32(addr, value);
507 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
509 *vstart = CONFIG_SYS_SDRAM_BASE;
511 /* we go up to relocation plus a 1 MB margin */
512 *size = CONFIG_SYS_TEXT_BASE - (1<<20);
518 #if defined(CONFIG_SYS_EEPROM_WREN)
519 int eeprom_write_enable(unsigned dev_addr, int state)
521 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
523 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);