3 * Marvell Semiconductor <www.marvell.com>
4 * Prafulla Wadaskar <prafulla@marvell.com>
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
10 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
12 * SPDX-License-Identifier: GPL-2.0+
22 #include <asm/arch/cpu.h>
23 #include <asm/arch/soc.h>
24 #include <asm/arch/mpp.h>
26 #include "../common/common.h"
28 DECLARE_GLOBAL_DATA_PTR;
31 * BOCO FPGA definitions
34 #define REG_CTRL_H 0x02
35 #define MASK_WRL_UNITRUN 0x01
36 #define MASK_RBX_PGY_PRESENT 0x40
37 #define REG_IRQ_CIRQ2 0x2d
38 #define MASK_RBI_DEFECT_16 0x01
41 * PHY registers definitions
43 #define PHY_MARVELL_OUI 0x5043
44 #define PHY_MARVELL_88E1118_MODEL 0x0022
45 #define PHY_MARVELL_88E1118R_MODEL 0x0024
47 #define PHY_MARVELL_PAGE_REG 0x0016
48 #define PHY_MARVELL_DEFAULT_PAGE 0x0000
50 #define PHY_MARVELL_88E1118R_LED_CTRL_PAGE 0x0003
51 #define PHY_MARVELL_88E1118R_LED_CTRL_REG 0x0010
53 #define PHY_MARVELL_88E1118R_LED_CTRL_RESERVED 0x1000
54 #define PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB (0x7<<0)
55 #define PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT (0x3<<4)
56 #define PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK (0x0<<8)
58 /* I/O pin to erase flash RGPP09 = MPP43 */
59 #define KM_FLASH_ERASE_ENABLE 43
61 /* Multi-Purpose Pins Functionality configuration */
62 static const u32 kwmpp_config[] = {
70 #if defined(KM_PCIE_RESET_MPP7)
75 #if defined(CONFIG_SYS_I2C_SOFT)
79 #if defined(CONFIG_HARD_I2C)
85 MPP12_GPO, /* Reserved */
88 MPP15_GPIO, /* Not used */
89 MPP16_GPIO, /* Not used */
90 MPP17_GPIO, /* Reserved */
107 MPP34_GPIO, /* CDL1 (input) */
108 MPP35_GPIO, /* CDL2 (input) */
109 MPP36_GPIO, /* MAIN_IRQ (input) */
110 MPP37_GPIO, /* BOARD_LED */
111 MPP38_GPIO, /* Piggy3 LED[1] */
112 MPP39_GPIO, /* Piggy3 LED[2] */
113 MPP40_GPIO, /* Piggy3 LED[3] */
114 MPP41_GPIO, /* Piggy3 LED[4] */
115 MPP42_GPIO, /* Piggy3 LED[5] */
116 MPP43_GPIO, /* Piggy3 LED[6] */
117 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */
118 MPP45_GPIO, /* Piggy3 LED[8] */
119 MPP46_GPIO, /* Reserved */
120 MPP47_GPIO, /* Reserved */
121 MPP48_GPIO, /* Reserved */
122 MPP49_GPIO, /* SW_INTOUTn */
126 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
128 #if defined(CONFIG_KM_MGCOGE3UN)
130 * Wait for startup OK from mgcoge3ne
132 static int startup_allowed(void)
137 * Read CIRQ16 bit (bit 0)
139 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
140 printf("%s: Error reading Boco\n", __func__);
142 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
148 #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
150 * All boards with PIGGY4 connected via a simple switch have ethernet always
153 int ethernet_present(void)
158 int ethernet_present(void)
163 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
164 printf("%s: Error reading Boco\n", __func__);
167 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
174 static int initialize_unit_leds(void)
177 * Init the unit LEDs per default they all are
178 * ok apart from bootstat
182 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
183 printf("%s: Error reading Boco\n", __func__);
186 buf |= MASK_WRL_UNITRUN;
187 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
188 printf("%s: Error writing Boco\n", __func__);
194 static void set_bootcount_addr(void)
197 unsigned int bootcountaddr;
198 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
199 sprintf((char *)buf, "0x%x", bootcountaddr);
200 setenv("bootcountaddr", (char *)buf);
203 int misc_init_r(void)
205 #if defined(CONFIG_KM_MGCOGE3UN)
207 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
208 wait_for_ne = getenv("waitforne");
210 if ((wait_for_ne != NULL) && (dip_switch == 0)) {
211 if (strcmp(wait_for_ne, "true") == 0) {
215 while (startup_allowed() == 0) {
217 (void) getc(); /* consume input */
224 puts("wait\b\b\b\b");
231 printf("\nAbort waiting for ne\n");
238 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
240 initialize_unit_leds();
242 set_bootcount_addr();
246 int board_early_init_f(void)
248 #if defined(CONFIG_SYS_I2C_SOFT)
251 /* set the 2 bitbang i2c pins as output gpios */
252 tmp = readl(MVEBU_GPIO0_BASE + 4);
253 writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4);
255 /* adjust SDRAM size for bank 0 */
256 mvebu_sdram_size_adjust(0);
257 kirkwood_mpp_conf(kwmpp_config, NULL);
263 /* address of boot parameters */
264 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
267 * The KM_FLASH_GPIO_PIN switches between using a
268 * NAND or a SPI FLASH. Set this pin on start
271 kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
272 kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
274 #if defined(CONFIG_SYS_I2C_SOFT)
276 * Reinit the GPIO for I2C Bitbang driver so that the now
277 * available gpio framework is consistent. The calls to
278 * direction output in are not necessary, they are already done in
281 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
282 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
285 #if defined(CONFIG_SYS_EEPROM_WREN)
286 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
287 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
290 #if defined(CONFIG_KM_FPGA_CONFIG)
291 trigger_fpga_config();
297 int board_late_init(void)
299 #if (defined(CONFIG_KM_COGE5UN) | defined(CONFIG_KM_MGCOGE3UN))
300 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
302 /* if pin 1 do full erase */
303 if (dip_switch != 0) {
304 /* start bootloader */
305 puts("DIP: Enabled\n");
306 setenv("actual_bank", "0");
310 #if defined(CONFIG_KM_FPGA_CONFIG)
311 wait_for_fpga_config();
313 toggle_eeprom_spi_bus();
318 int board_spi_claim_bus(struct spi_slave *slave)
320 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
325 void board_spi_release_bus(struct spi_slave *slave)
327 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
330 #if (defined(CONFIG_KM_PIGGY4_88E6061))
332 #define PHY_LED_SEL_REG 0x18
333 #define PHY_LED0_LINK (0x5)
334 #define PHY_LED1_ACT (0x8<<4)
335 #define PHY_LED2_INT (0xe<<8)
336 #define PHY_SPEC_CTRL_REG 0x1c
337 #define PHY_RGMII_CLK_STABLE (0x1<<10)
338 #define PHY_CLSA (0x1<<1)
340 /* Configure and enable MV88E3018 PHY */
343 char *name = "egiga0";
346 if (miiphy_set_current_dev(name))
349 /* RGMII clk transition on data stable */
350 if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®))
351 printf("Error reading PHY spec ctrl reg\n");
352 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
353 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
354 printf("Error writing PHY spec ctrl reg\n");
357 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
358 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
359 printf("Error writing PHY LED reg\n");
362 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
364 #elif defined(CONFIG_KM_PIGGY4_88E6352)
366 #include <mv88e6352.h>
368 #if defined(CONFIG_KM_NUSA)
369 struct mv88e_sw_reg extsw_conf[] = {
371 * port 0, PIGGY4, autoneg
372 * first the fix for the 1000Mbits Autoneg, this is from
373 * a Marvell errata, the regs are undocumented
375 { PHY(0), PHY_PAGE, AN1000FIX_PAGE },
376 { PHY(0), PHY_STATUS, AN1000FIX },
377 { PHY(0), PHY_PAGE, 0 },
378 /* now the real port and phy configuration */
379 { PORT(0), PORT_PHY, NO_SPEED_FOR },
380 { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
381 { PHY(0), PHY_1000_CTRL, NO_ADV },
382 { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
383 { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
386 { PORT(1), PORT_CTRL, PORT_DIS },
387 { PHY(1), PHY_CTRL, PHY_PWR_DOWN },
388 { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
390 { PORT(2), PORT_CTRL, PORT_DIS },
391 { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
392 { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
394 { PORT(3), PORT_CTRL, PORT_DIS },
395 { PHY(3), PHY_CTRL, PHY_PWR_DOWN },
396 { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
397 /* port 4, ICNEV, SerDes, SGMII */
398 { PORT(4), PORT_STATUS, NO_PHY_DETECT },
399 { PORT(4), PORT_PHY, SPEED_1000_FOR },
400 { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
401 { PHY(4), PHY_CTRL, PHY_PWR_DOWN },
402 { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
403 /* port 5, CPU_RGMII */
404 { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
405 FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
406 FULL_DPX_FOR | SPEED_1000_FOR },
407 { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
408 /* port 6, unused, this port has no phy */
409 { PORT(6), PORT_CTRL, PORT_DIS },
412 struct mv88e_sw_reg extsw_conf[] = {};
417 #if defined(CONFIG_KM_MVEXTSW_ADDR)
418 char *name = "egiga0";
420 if (miiphy_set_current_dev(name))
423 mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
424 ARRAY_SIZE(extsw_conf));
425 mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
430 /* Configure and enable MV88E1118 PHY on the piggy*/
434 unsigned char model, rev;
436 char *name = "egiga0";
438 if (miiphy_set_current_dev(name))
442 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
445 if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev))
448 /* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */
449 if ((oui == PHY_MARVELL_OUI) &&
450 (model == PHY_MARVELL_88E1118R_MODEL)) {
451 /* set page register to 3 */
452 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
453 PHY_MARVELL_PAGE_REG,
454 PHY_MARVELL_88E1118R_LED_CTRL_PAGE))
455 printf("Error writing PHY page reg\n");
458 * leds setup as printed on PCB:
459 * LED2 (Link): 0x0 (On Link, Off No Link)
460 * LED1 (Activity): 0x3 (On Activity, Off No Activity)
461 * LED0 (Speed): 0x7 (On 1000 MBits, Off Else)
463 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
464 PHY_MARVELL_88E1118R_LED_CTRL_REG,
465 PHY_MARVELL_88E1118R_LED_CTRL_RESERVED |
466 PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB |
467 PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT |
468 PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK))
469 printf("Error writing PHY LED reg\n");
471 /* set page register back to 0 */
472 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
473 PHY_MARVELL_PAGE_REG,
474 PHY_MARVELL_DEFAULT_PAGE))
475 printf("Error writing PHY page reg\n");
481 #if defined(CONFIG_HUSH_INIT_VAR)
482 int hush_init_var(void)
484 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
489 #if defined(CONFIG_SYS_I2C_SOFT)
490 void set_sda(int state)
496 void set_scl(int state)
509 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
513 #if defined(CONFIG_POST)
515 #define KM_POST_EN_L 44
516 #define POST_WORD_OFF 8
518 int post_hotkeys_pressed(void)
520 #if defined(CONFIG_KM_COGE5UN)
521 return kw_gpio_get_value(KM_POST_EN_L);
523 return !kw_gpio_get_value(KM_POST_EN_L);
527 ulong post_word_load(void)
529 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
530 return in_le32(addr);
533 void post_word_store(ulong value)
535 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
536 out_le32(addr, value);
539 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
541 *vstart = CONFIG_SYS_SDRAM_BASE;
543 /* we go up to relocation plus a 1 MB margin */
544 *size = CONFIG_SYS_TEXT_BASE - (1<<20);
550 #if defined(CONFIG_SYS_EEPROM_WREN)
551 int eeprom_write_enable(unsigned dev_addr, int state)
553 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
555 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);