3 * Marvell Semiconductor <www.marvell.com>
4 * Prafulla Wadaskar <prafulla@marvell.com>
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
10 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
12 * SPDX-License-Identifier: GPL-2.0+
22 #include <asm/arch/cpu.h>
23 #include <asm/arch/soc.h>
24 #include <asm/arch/mpp.h>
26 #include "../common/common.h"
28 DECLARE_GLOBAL_DATA_PTR;
31 * BOCO FPGA definitions
34 #define REG_CTRL_H 0x02
35 #define MASK_WRL_UNITRUN 0x01
36 #define MASK_RBX_PGY_PRESENT 0x40
37 #define REG_IRQ_CIRQ2 0x2d
38 #define MASK_RBI_DEFECT_16 0x01
41 * PHY registers definitions
43 #define PHY_MARVELL_OUI 0x5043
44 #define PHY_MARVELL_88E1118_MODEL 0x0022
45 #define PHY_MARVELL_88E1118R_MODEL 0x0024
47 #define PHY_MARVELL_PAGE_REG 0x0016
48 #define PHY_MARVELL_DEFAULT_PAGE 0x0000
50 #define PHY_MARVELL_88E1118R_LED_CTRL_PAGE 0x0003
51 #define PHY_MARVELL_88E1118R_LED_CTRL_REG 0x0010
53 #define PHY_MARVELL_88E1118R_LED_CTRL_RESERVED 0x1000
54 #define PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB (0x7<<0)
55 #define PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT (0x3<<4)
56 #define PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK (0x0<<8)
58 /* Multi-Purpose Pins Functionality configuration */
59 static const u32 kwmpp_config[] = {
67 #if defined(KM_PCIE_RESET_MPP7)
72 #if defined(CONFIG_SYS_I2C_SOFT)
76 #if defined(CONFIG_HARD_I2C)
82 MPP12_GPO, /* Reserved */
85 MPP15_GPIO, /* Not used */
86 MPP16_GPIO, /* Not used */
87 MPP17_GPIO, /* Reserved */
104 MPP34_GPIO, /* CDL1 (input) */
105 MPP35_GPIO, /* CDL2 (input) */
106 MPP36_GPIO, /* MAIN_IRQ (input) */
107 MPP37_GPIO, /* BOARD_LED */
108 MPP38_GPIO, /* Piggy3 LED[1] */
109 MPP39_GPIO, /* Piggy3 LED[2] */
110 MPP40_GPIO, /* Piggy3 LED[3] */
111 MPP41_GPIO, /* Piggy3 LED[4] */
112 MPP42_GPIO, /* Piggy3 LED[5] */
113 MPP43_GPIO, /* Piggy3 LED[6] */
114 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */
115 MPP45_GPIO, /* Piggy3 LED[8] */
116 MPP46_GPIO, /* Reserved */
117 MPP47_GPIO, /* Reserved */
118 MPP48_GPIO, /* Reserved */
119 MPP49_GPIO, /* SW_INTOUTn */
123 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
125 #if defined(CONFIG_KM_MGCOGE3UN)
127 * Wait for startup OK from mgcoge3ne
129 static int startup_allowed(void)
134 * Read CIRQ16 bit (bit 0)
136 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
137 printf("%s: Error reading Boco\n", __func__);
139 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
145 #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
147 * All boards with PIGGY4 connected via a simple switch have ethernet always
150 int ethernet_present(void)
155 int ethernet_present(void)
160 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
161 printf("%s: Error reading Boco\n", __func__);
164 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
171 static int initialize_unit_leds(void)
174 * Init the unit LEDs per default they all are
175 * ok apart from bootstat
179 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
180 printf("%s: Error reading Boco\n", __func__);
183 buf |= MASK_WRL_UNITRUN;
184 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
185 printf("%s: Error writing Boco\n", __func__);
191 static void set_bootcount_addr(void)
194 unsigned int bootcountaddr;
195 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
196 sprintf((char *)buf, "0x%x", bootcountaddr);
197 setenv("bootcountaddr", (char *)buf);
200 int misc_init_r(void)
202 #if defined(CONFIG_KM_MGCOGE3UN)
204 wait_for_ne = getenv("waitforne");
205 if (wait_for_ne != NULL) {
206 if (strcmp(wait_for_ne, "true") == 0) {
210 while (startup_allowed() == 0) {
212 (void) getc(); /* consume input */
219 puts("wait\b\b\b\b");
226 printf("\nAbort waiting for ne\n");
233 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
235 initialize_unit_leds();
237 set_bootcount_addr();
241 int board_early_init_f(void)
243 #if defined(CONFIG_SYS_I2C_SOFT)
246 /* set the 2 bitbang i2c pins as output gpios */
247 tmp = readl(MVEBU_GPIO0_BASE + 4);
248 writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4);
250 /* adjust SDRAM size for bank 0 */
251 mvebu_sdram_size_adjust(0);
252 kirkwood_mpp_conf(kwmpp_config, NULL);
258 /* address of boot parameters */
259 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
262 * The KM_FLASH_GPIO_PIN switches between using a
263 * NAND or a SPI FLASH. Set this pin on start
266 kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
267 kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
269 #if defined(CONFIG_SYS_I2C_SOFT)
271 * Reinit the GPIO for I2C Bitbang driver so that the now
272 * available gpio framework is consistent. The calls to
273 * direction output in are not necessary, they are already done in
276 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
277 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
280 #if defined(CONFIG_SYS_EEPROM_WREN)
281 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
282 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
285 #if defined(CONFIG_KM_FPGA_CONFIG)
286 trigger_fpga_config();
292 int board_late_init(void)
294 #if defined(CONFIG_KMCOGE5UN)
295 /* I/O pin to erase flash RGPP09 = MPP43 */
296 #define KM_FLASH_ERASE_ENABLE 43
297 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
299 /* if pin 1 do full erase */
300 if (dip_switch != 0) {
301 /* start bootloader */
302 puts("DIP: Enabled\n");
303 setenv("actual_bank", "0");
307 #if defined(CONFIG_KM_FPGA_CONFIG)
308 wait_for_fpga_config();
310 toggle_eeprom_spi_bus();
315 int board_spi_claim_bus(struct spi_slave *slave)
317 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
322 void board_spi_release_bus(struct spi_slave *slave)
324 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
327 #if (defined(CONFIG_KM_PIGGY4_88E6061))
329 #define PHY_LED_SEL_REG 0x18
330 #define PHY_LED0_LINK (0x5)
331 #define PHY_LED1_ACT (0x8<<4)
332 #define PHY_LED2_INT (0xe<<8)
333 #define PHY_SPEC_CTRL_REG 0x1c
334 #define PHY_RGMII_CLK_STABLE (0x1<<10)
335 #define PHY_CLSA (0x1<<1)
337 /* Configure and enable MV88E3018 PHY */
340 char *name = "egiga0";
343 if (miiphy_set_current_dev(name))
346 /* RGMII clk transition on data stable */
347 if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®))
348 printf("Error reading PHY spec ctrl reg\n");
349 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
350 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
351 printf("Error writing PHY spec ctrl reg\n");
354 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
355 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
356 printf("Error writing PHY LED reg\n");
359 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
361 #elif defined(CONFIG_KM_PIGGY4_88E6352)
363 #include <mv88e6352.h>
365 #if defined(CONFIG_KM_NUSA)
366 struct mv88e_sw_reg extsw_conf[] = {
368 * port 0, PIGGY4, autoneg
369 * first the fix for the 1000Mbits Autoneg, this is from
370 * a Marvell errata, the regs are undocumented
372 { PHY(0), PHY_PAGE, AN1000FIX_PAGE },
373 { PHY(0), PHY_STATUS, AN1000FIX },
374 { PHY(0), PHY_PAGE, 0 },
375 /* now the real port and phy configuration */
376 { PORT(0), PORT_PHY, NO_SPEED_FOR },
377 { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
378 { PHY(0), PHY_1000_CTRL, NO_ADV },
379 { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
380 { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
383 { PORT(1), PORT_CTRL, PORT_DIS },
384 { PHY(1), PHY_CTRL, PHY_PWR_DOWN },
385 { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
387 { PORT(2), PORT_CTRL, PORT_DIS },
388 { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
389 { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
391 { PORT(3), PORT_CTRL, PORT_DIS },
392 { PHY(3), PHY_CTRL, PHY_PWR_DOWN },
393 { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
394 /* port 4, ICNEV, SerDes, SGMII */
395 { PORT(4), PORT_STATUS, NO_PHY_DETECT },
396 { PORT(4), PORT_PHY, SPEED_1000_FOR },
397 { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
398 { PHY(4), PHY_CTRL, PHY_PWR_DOWN },
399 { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
400 /* port 5, CPU_RGMII */
401 { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
402 FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
403 FULL_DPX_FOR | SPEED_1000_FOR },
404 { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
405 /* port 6, unused, this port has no phy */
406 { PORT(6), PORT_CTRL, PORT_DIS },
409 struct mv88e_sw_reg extsw_conf[] = {};
414 #if defined(CONFIG_KM_MVEXTSW_ADDR)
415 char *name = "egiga0";
417 if (miiphy_set_current_dev(name))
420 mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
421 ARRAY_SIZE(extsw_conf));
422 mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
427 /* Configure and enable MV88E1118 PHY on the piggy*/
431 unsigned char model, rev;
433 char *name = "egiga0";
435 if (miiphy_set_current_dev(name))
439 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
442 if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev))
445 /* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */
446 if ((oui == PHY_MARVELL_OUI) &&
447 (model == PHY_MARVELL_88E1118R_MODEL)) {
448 /* set page register to 3 */
449 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
450 PHY_MARVELL_PAGE_REG,
451 PHY_MARVELL_88E1118R_LED_CTRL_PAGE))
452 printf("Error writing PHY page reg\n");
455 * leds setup as printed on PCB:
456 * LED2 (Link): 0x0 (On Link, Off No Link)
457 * LED1 (Activity): 0x3 (On Activity, Off No Activity)
458 * LED0 (Speed): 0x7 (On 1000 MBits, Off Else)
460 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
461 PHY_MARVELL_88E1118R_LED_CTRL_REG,
462 PHY_MARVELL_88E1118R_LED_CTRL_RESERVED |
463 PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB |
464 PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT |
465 PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK))
466 printf("Error writing PHY LED reg\n");
468 /* set page register back to 0 */
469 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
470 PHY_MARVELL_PAGE_REG,
471 PHY_MARVELL_DEFAULT_PAGE))
472 printf("Error writing PHY page reg\n");
478 #if defined(CONFIG_HUSH_INIT_VAR)
479 int hush_init_var(void)
481 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
486 #if defined(CONFIG_SYS_I2C_SOFT)
487 void set_sda(int state)
493 void set_scl(int state)
506 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
510 #if defined(CONFIG_POST)
512 #define KM_POST_EN_L 44
513 #define POST_WORD_OFF 8
515 int post_hotkeys_pressed(void)
517 #if defined(CONFIG_KM_COGE5UN)
518 return kw_gpio_get_value(KM_POST_EN_L);
520 return !kw_gpio_get_value(KM_POST_EN_L);
524 ulong post_word_load(void)
526 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
527 return in_le32(addr);
530 void post_word_store(ulong value)
532 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
533 out_le32(addr, value);
536 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
538 *vstart = CONFIG_SYS_SDRAM_BASE;
540 /* we go up to relocation plus a 1 MB margin */
541 *size = CONFIG_SYS_TEXT_BASE - (1<<20);
547 #if defined(CONFIG_SYS_EEPROM_WREN)
548 int eeprom_write_enable(unsigned dev_addr, int state)
550 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
552 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);