1 // SPDX-License-Identifier: GPL-2.0+
4 * Marvell Semiconductor <www.marvell.com>
5 * Prafulla Wadaskar <prafulla@marvell.com>
8 * Stefan Roese, DENX Software Engineering, sr@denx.de.
11 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
21 #include <asm/arch/cpu.h>
22 #include <asm/arch/soc.h>
23 #include <asm/arch/mpp.h>
25 #include "../common/common.h"
27 DECLARE_GLOBAL_DATA_PTR;
30 * BOCO FPGA definitions
33 #define REG_CTRL_H 0x02
34 #define MASK_WRL_UNITRUN 0x01
35 #define MASK_RBX_PGY_PRESENT 0x40
36 #define REG_IRQ_CIRQ2 0x2d
37 #define MASK_RBI_DEFECT_16 0x01
40 * PHY registers definitions
42 #define PHY_MARVELL_OUI 0x5043
43 #define PHY_MARVELL_88E1118_MODEL 0x0022
44 #define PHY_MARVELL_88E1118R_MODEL 0x0024
46 #define PHY_MARVELL_PAGE_REG 0x0016
47 #define PHY_MARVELL_DEFAULT_PAGE 0x0000
49 #define PHY_MARVELL_88E1118R_LED_CTRL_PAGE 0x0003
50 #define PHY_MARVELL_88E1118R_LED_CTRL_REG 0x0010
52 #define PHY_MARVELL_88E1118R_LED_CTRL_RESERVED 0x1000
53 #define PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB (0x7<<0)
54 #define PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT (0x3<<4)
55 #define PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK (0x0<<8)
57 /* I/O pin to erase flash RGPP09 = MPP43 */
58 #define KM_FLASH_ERASE_ENABLE 43
60 /* Multi-Purpose Pins Functionality configuration */
61 static const u32 kwmpp_config[] = {
69 #if defined(KM_PCIE_RESET_MPP7)
74 #if defined(CONFIG_SYS_I2C_SOFT)
80 MPP12_GPO, /* Reserved */
83 MPP15_GPIO, /* Not used */
84 MPP16_GPIO, /* Not used */
85 MPP17_GPIO, /* Reserved */
102 MPP34_GPIO, /* CDL1 (input) */
103 MPP35_GPIO, /* CDL2 (input) */
104 MPP36_GPIO, /* MAIN_IRQ (input) */
105 MPP37_GPIO, /* BOARD_LED */
106 MPP38_GPIO, /* Piggy3 LED[1] */
107 MPP39_GPIO, /* Piggy3 LED[2] */
108 MPP40_GPIO, /* Piggy3 LED[3] */
109 MPP41_GPIO, /* Piggy3 LED[4] */
110 MPP42_GPIO, /* Piggy3 LED[5] */
111 MPP43_GPIO, /* Piggy3 LED[6] */
112 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */
113 MPP45_GPIO, /* Piggy3 LED[8] */
114 MPP46_GPIO, /* Reserved */
115 MPP47_GPIO, /* Reserved */
116 MPP48_GPIO, /* Reserved */
117 MPP49_GPIO, /* SW_INTOUTn */
121 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
123 #if defined(CONFIG_KM_MGCOGE3UN)
125 * Wait for startup OK from mgcoge3ne
127 static int startup_allowed(void)
132 * Read CIRQ16 bit (bit 0)
134 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
135 printf("%s: Error reading Boco\n", __func__);
137 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
143 #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
145 * All boards with PIGGY4 connected via a simple switch have ethernet always
148 int ethernet_present(void)
153 int ethernet_present(void)
158 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
159 printf("%s: Error reading Boco\n", __func__);
162 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
169 static int initialize_unit_leds(void)
172 * Init the unit LEDs per default they all are
173 * ok apart from bootstat
177 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
178 printf("%s: Error reading Boco\n", __func__);
181 buf |= MASK_WRL_UNITRUN;
182 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
183 printf("%s: Error writing Boco\n", __func__);
189 static void set_bootcount_addr(void)
192 unsigned int bootcountaddr;
193 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
194 sprintf((char *)buf, "0x%x", bootcountaddr);
195 env_set("bootcountaddr", (char *)buf);
198 int misc_init_r(void)
200 #if defined(CONFIG_KM_MGCOGE3UN)
202 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
203 wait_for_ne = env_get("waitforne");
205 if ((wait_for_ne != NULL) && (dip_switch == 0)) {
206 if (strcmp(wait_for_ne, "true") == 0) {
210 while (startup_allowed() == 0) {
212 (void) getc(); /* consume input */
219 puts("wait\b\b\b\b");
226 printf("\nAbort waiting for ne\n");
233 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
235 initialize_unit_leds();
237 set_bootcount_addr();
241 int board_early_init_f(void)
243 #if defined(CONFIG_SYS_I2C_SOFT)
246 /* set the 2 bitbang i2c pins as output gpios */
247 tmp = readl(MVEBU_GPIO0_BASE + 4);
248 writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4);
250 /* adjust SDRAM size for bank 0 */
251 mvebu_sdram_size_adjust(0);
252 kirkwood_mpp_conf(kwmpp_config, NULL);
258 /* address of boot parameters */
259 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
262 * The KM_FLASH_GPIO_PIN switches between using a
263 * NAND or a SPI FLASH. Set this pin on start
266 kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
267 kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
269 #if defined(CONFIG_SYS_I2C_SOFT)
271 * Reinit the GPIO for I2C Bitbang driver so that the now
272 * available gpio framework is consistent. The calls to
273 * direction output in are not necessary, they are already done in
276 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
277 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
280 #if defined(CONFIG_SYS_EEPROM_WREN)
281 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
282 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
285 #if defined(CONFIG_KM_FPGA_CONFIG)
286 trigger_fpga_config();
292 int board_late_init(void)
294 #if (defined(CONFIG_KM_COGE5UN) | defined(CONFIG_KM_MGCOGE3UN))
295 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
297 /* if pin 1 do full erase */
298 if (dip_switch != 0) {
299 /* start bootloader */
300 puts("DIP: Enabled\n");
301 env_set("actual_bank", "0");
305 #if defined(CONFIG_KM_FPGA_CONFIG)
306 wait_for_fpga_config();
308 toggle_eeprom_spi_bus();
313 int board_spi_claim_bus(struct spi_slave *slave)
315 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
320 void board_spi_release_bus(struct spi_slave *slave)
322 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
325 #if (defined(CONFIG_KM_PIGGY4_88E6061))
327 #define PHY_LED_SEL_REG 0x18
328 #define PHY_LED0_LINK (0x5)
329 #define PHY_LED1_ACT (0x8<<4)
330 #define PHY_LED2_INT (0xe<<8)
331 #define PHY_SPEC_CTRL_REG 0x1c
332 #define PHY_RGMII_CLK_STABLE (0x1<<10)
333 #define PHY_CLSA (0x1<<1)
335 /* Configure and enable MV88E3018 PHY */
338 char *name = "egiga0";
341 if (miiphy_set_current_dev(name))
344 /* RGMII clk transition on data stable */
345 if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®))
346 printf("Error reading PHY spec ctrl reg\n");
347 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
348 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
349 printf("Error writing PHY spec ctrl reg\n");
352 if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
353 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
354 printf("Error writing PHY LED reg\n");
357 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
359 #elif defined(CONFIG_KM_PIGGY4_88E6352)
361 #include <mv88e6352.h>
363 #if defined(CONFIG_KM_NUSA)
364 struct mv88e_sw_reg extsw_conf[] = {
366 * port 0, PIGGY4, autoneg
367 * first the fix for the 1000Mbits Autoneg, this is from
368 * a Marvell errata, the regs are undocumented
370 { PHY(0), PHY_PAGE, AN1000FIX_PAGE },
371 { PHY(0), PHY_STATUS, AN1000FIX },
372 { PHY(0), PHY_PAGE, 0 },
373 /* now the real port and phy configuration */
374 { PORT(0), PORT_PHY, NO_SPEED_FOR },
375 { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
376 { PHY(0), PHY_1000_CTRL, NO_ADV },
377 { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
378 { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
381 { PORT(1), PORT_CTRL, PORT_DIS },
382 { PHY(1), PHY_CTRL, PHY_PWR_DOWN },
383 { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
385 { PORT(2), PORT_CTRL, PORT_DIS },
386 { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
387 { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
389 { PORT(3), PORT_CTRL, PORT_DIS },
390 { PHY(3), PHY_CTRL, PHY_PWR_DOWN },
391 { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
392 /* port 4, ICNEV, SerDes, SGMII */
393 { PORT(4), PORT_STATUS, NO_PHY_DETECT },
394 { PORT(4), PORT_PHY, SPEED_1000_FOR },
395 { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
396 { PHY(4), PHY_CTRL, PHY_PWR_DOWN },
397 { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
398 /* port 5, CPU_RGMII */
399 { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
400 FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
401 FULL_DPX_FOR | SPEED_1000_FOR },
402 { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
403 /* port 6, unused, this port has no phy */
404 { PORT(6), PORT_CTRL, PORT_DIS },
407 struct mv88e_sw_reg extsw_conf[] = {};
412 #if defined(CONFIG_KM_MVEXTSW_ADDR)
413 char *name = "egiga0";
415 if (miiphy_set_current_dev(name))
418 mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
419 ARRAY_SIZE(extsw_conf));
420 mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
425 /* Configure and enable MV88E1118 PHY on the piggy*/
429 unsigned char model, rev;
431 char *name = "egiga0";
433 if (miiphy_set_current_dev(name))
437 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
440 if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev))
443 /* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */
444 if ((oui == PHY_MARVELL_OUI) &&
445 (model == PHY_MARVELL_88E1118R_MODEL)) {
446 /* set page register to 3 */
447 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
448 PHY_MARVELL_PAGE_REG,
449 PHY_MARVELL_88E1118R_LED_CTRL_PAGE))
450 printf("Error writing PHY page reg\n");
453 * leds setup as printed on PCB:
454 * LED2 (Link): 0x0 (On Link, Off No Link)
455 * LED1 (Activity): 0x3 (On Activity, Off No Activity)
456 * LED0 (Speed): 0x7 (On 1000 MBits, Off Else)
458 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
459 PHY_MARVELL_88E1118R_LED_CTRL_REG,
460 PHY_MARVELL_88E1118R_LED_CTRL_RESERVED |
461 PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB |
462 PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT |
463 PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK))
464 printf("Error writing PHY LED reg\n");
466 /* set page register back to 0 */
467 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
468 PHY_MARVELL_PAGE_REG,
469 PHY_MARVELL_DEFAULT_PAGE))
470 printf("Error writing PHY page reg\n");
476 #if defined(CONFIG_HUSH_INIT_VAR)
477 int hush_init_var(void)
479 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
484 #if defined(CONFIG_SYS_I2C_SOFT)
485 void set_sda(int state)
491 void set_scl(int state)
504 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
508 #if defined(CONFIG_POST)
510 #define KM_POST_EN_L 44
511 #define POST_WORD_OFF 8
513 int post_hotkeys_pressed(void)
515 #if defined(CONFIG_KM_COGE5UN)
516 return kw_gpio_get_value(KM_POST_EN_L);
518 return !kw_gpio_get_value(KM_POST_EN_L);
522 ulong post_word_load(void)
524 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
525 return in_le32(addr);
528 void post_word_store(ulong value)
530 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
531 out_le32(addr, value);
534 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
536 *vstart = CONFIG_SYS_SDRAM_BASE;
538 /* we go up to relocation plus a 1 MB margin */
539 *size = CONFIG_SYS_TEXT_BASE - (1<<20);
545 #if defined(CONFIG_SYS_EEPROM_WREN)
546 int eeprom_write_enable(unsigned dev_addr, int state)
548 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
550 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);