3 # Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 # See file CREDITS for list of people who contributed to this
8 # This program is free software; you can redistribute it and/or
9 # modify it under the terms of the GNU General Public License as
10 # published by the Free Software Foundation; either version 2 of
11 # the License, or (at your option) any later version.
13 # This program is distributed in the hope that it will be useful,
14 # but WITHOUT ANY WARRANTY; without even the implied warranty of
15 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 # GNU General Public License for more details.
18 # You should have received a copy of the GNU General Public License
19 # along with this program; if not, write to the Free Software
20 # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
23 # Refer docs/README.kwimage for more details about how-to configure
24 # and create kirkwood boot image
27 # Boot Media configurations
28 BOOT_FROM spi # Boot from SPI flash
30 DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
31 # bit 3-0: MPPSel0 2, NF_IO[2]
32 # bit 7-4: MPPSel1 2, NF_IO[3]
33 # bit 12-8: MPPSel2 2, NF_IO[4]
34 # bit 15-12: MPPSel3 2, NF_IO[5]
35 # bit 19-16: MPPSel4 1, NF_IO[6]
36 # bit 23-20: MPPSel5 1, NF_IO[7]
37 # bit 27-24: MPPSel6 1, SYSRST_O
38 # bit 31-28: MPPSel7 0, GPO[7]
40 DATA 0xFFD10004 0x03303300
42 DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
43 # bit 3-0: MPPSel16 0, GPIO[16]
44 # bit 7-4: MPPSel17 0, GPIO[17]
45 # bit 12-8: MPPSel18 1, NF_IO[0]
46 # bit 15-12: MPPSel19 1, NF_IO[1]
47 # bit 19-16: MPPSel20 0, GPIO[20]
48 # bit 23-20: MPPSel21 0, GPIO[21]
49 # bit 27-24: MPPSel22 0, GPIO[22]
50 # bit 31-28: MPPSel23 0, GPIO[23]
52 DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
53 DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
54 DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
56 # NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
57 # If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
60 DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register
61 # bit13-0: 0x400 (DDR2 clks refresh rate)
63 # bit24: 1= enable exit self refresh mode on DDR access
68 DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
70 # bit 4: 0=addr/cmd in smame cycle
71 # bit 5: 0=clk is driven during self refresh, we don't care for APX
72 # bit 6: 0=use recommended falling edge of clk for addr/cmd
73 # bit14: 0=input buffer always powered up
74 # bit18: 1=cpu lock transaction enabled
75 # bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0
76 # bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
77 # bit30-28: 3 required
78 # bit31: 0=no additional STARTBURST delay
80 DATA 0xFFD01408 0x34136552 # DDR Timing (Low) (active cycles value +1)
91 DATA 0xFFD0140C 0x00000033 # DDR Timing (High)
96 # bit31-13: zero required
98 DATA 0xFFD01410 0x0000000D # DDR Address Control
99 # bit1-0: 01, Cs0width=x16
100 # bit3-2: 11, Cs0size=1Gb
101 # bit5-4: 00, Cs2width=nonexistent
102 # bit7-6: 00, Cs1size =nonexistent
103 # bit9-8: 00, Cs2width=nonexistent
104 # bit11-10: 00, Cs2size =nonexistent
105 # bit13-12: 00, Cs3width=nonexistent
106 # bit15-14: 00, Cs3size =nonexistent
107 # bit16: 0, Cs0AddrSel
108 # bit17: 0, Cs1AddrSel
109 # bit18: 0, Cs2AddrSel
110 # bit19: 0, Cs3AddrSel
111 # bit31-20: 0 required
113 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
114 # bit0: 0, OpenPage enabled
115 # bit31-1: 0 required
117 DATA 0xFFD01418 0x00000000 # DDR Operation
118 # bit3-0: 0x0, DDR cmd
119 # bit31-4: 0 required
121 DATA 0xFFD0141C 0x00000652 # DDR Mode
122 DATA 0xFFD01420 0x00000044 # DDR Extended Mode
123 # bit0: 0, DDR DLL enabled
124 # bit1: 0, DDR drive strenght normal
125 # bit2: 1, DDR ODT control lsd disabled
126 # bit5-3: 000, required
127 # bit6: 1, DDR ODT control msb, enabled
128 # bit9-7: 000, required
129 # bit10: 0, differential DQS enabled
131 # bit12: 0, DDR output buffer enabled
132 # bit31-13: 0 required
134 DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
135 # bit2-0: 111, required
136 # bit3 : 1 , MBUS Burst Chop disabled
137 # bit6-4: 111, required
139 # bit8 : 0 , no sample stage
140 # bit9 : 0 , no half clock cycle addition to dataout
141 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
142 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
143 # bit15-12: 1111 required
144 # bit31-16: 0 required
145 DATA 0xFFD01428 0x00074510
146 DATA 0xFFD0147c 0x00007451
148 DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
149 DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
150 # bit0: 1, Window enabled
151 # bit1: 0, Write Protect disabled
152 # bit3-2: 00, CS0 hit selected
153 # bit23-4: ones, required
154 # bit31-24: 0x07, Size (i.e. 128MB)
156 DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
157 DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
158 DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
160 DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low)
161 # bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0
162 # bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0
164 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
165 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
166 # bit3-2: 00, ODT1 controlled by register
167 # bit31-4: zero, required
169 DATA 0xFFD0149C 0x0000FC11 # CPU ODT Control
170 # bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0
171 # bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
172 # bit9-8: 1, ODTEn, never active
173 # bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
175 DATA 0xFFD01480 0x00000001 # DDR Initialization Control
176 # bit0=1, enable DDR init upon this register write
178 # End of Header extension