2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * Copyright (C) 2007 Logic Product Development, Inc.
6 * Peter Barada <peterb@logicpd.com>
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
12 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
27 #include <asm/processor.h>
31 #include "../common/common.h"
33 extern void disable_addr_trans (void);
34 extern void enable_addr_trans (void);
35 const qe_iop_conf_t qe_iop_conf_tab[] = {
36 /* port pin dir open_drain assign */
39 {0, 1, 3, 0, 2}, /* MDIO */
40 {0, 2, 1, 0, 1}, /* MDC */
43 {1, 14, 1, 0, 1}, /* TxD0 */
44 {1, 15, 1, 0, 1}, /* TxD1 */
45 {1, 20, 2, 0, 1}, /* RxD0 */
46 {1, 21, 2, 0, 1}, /* RxD1 */
47 {1, 18, 1, 0, 1}, /* TX_EN */
48 {1, 26, 2, 0, 1}, /* RX_DV */
49 {1, 27, 2, 0, 1}, /* RX_ER */
50 {1, 24, 2, 0, 1}, /* COL */
51 {1, 25, 2, 0, 1}, /* CRS */
52 {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
53 {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
56 {5, 0, 1, 0, 2}, /* UART2_SOUT */
57 {5, 2, 1, 0, 1}, /* UART2_RTS */
58 {5, 3, 2, 0, 2}, /* UART2_SIN */
59 {5, 1, 2, 0, 3}, /* UART2_CTS */
62 {0, 0, 0, 0, QE_IOP_TAB_END},
65 static int board_init_i2c_busses (void)
67 I2C_MUX_DEVICE *dev = NULL;
70 /* Set up the Bus for the DTTs */
71 buf = (unsigned char *) getenv ("dtt_bus");
73 dev = i2c_mux_ident_muxstring (buf);
75 printf ("Error couldn't add Bus for DTT\n");
76 printf ("please setup dtt_bus to where your\n");
77 printf ("DTT is found.\n");
82 int board_early_init_r (void)
87 * Because of errata in the UCCs, we have to write to the reserved
88 * registers to slow the clocks down.
90 svid = SVR_REV(mfspr (SVR));
93 setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
96 clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
97 0x00000050, 0x000000a0);
100 /* enable the PHY on the PIGGY */
101 setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x10003), 0x01);
106 int misc_init_r (void)
108 /* add board specific i2c busses */
109 board_init_i2c_busses ();
113 int fixed_sdram(void)
115 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
120 im->sysconf.ddrlaw[0].ar = LAWAR_EN | 0x1e;
121 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
122 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
123 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
124 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
125 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
126 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
127 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
128 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
129 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
130 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
131 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
132 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
134 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
136 msize = CONFIG_SYS_DDR_SIZE << 20;
137 disable_addr_trans ();
138 msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize);
139 enable_addr_trans ();
140 msize /= (1024 * 1024);
141 if (CONFIG_SYS_DDR_SIZE != msize) {
142 for (ddr_size = msize << 20, ddr_size_log2 = 0;
143 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++)
146 im->sysconf.ddrlaw[0].ar =
147 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
148 im->ddr.csbnds[0].csbnds = (((msize / 16) - 1) & 0xff);
154 phys_size_t initdram (int board_type)
156 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
157 extern void ddr_enable_ecc (unsigned int dram_size);
159 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
162 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
165 /* DDR SDRAM - Main SODIMM */
166 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
167 msize = fixed_sdram ();
169 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
171 * Initialize DDR ECC byte
173 ddr_enable_ecc (msize * 1024 * 1024);
176 /* return total bus SDRAM size(bytes) -- DDR */
177 return (msize * 1024 * 1024);
180 int checkboard (void)
182 puts ("Board: Keymile kmeter1");
183 if (ethernet_present ())
184 puts (" with PIGGY.");
189 #if defined(CONFIG_OF_BOARD_SETUP)
190 void ft_board_setup (void *blob, bd_t *bd)
192 ft_cpu_setup (blob, bd);
196 #if defined(CONFIG_HUSH_INIT_VAR)
197 extern int ivm_read_eeprom (void);
198 int hush_init_var (void)