2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * Copyright (C) 2007 Logic Product Development, Inc.
6 * Peter Barada <peterb@logicpd.com>
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
12 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
30 const qe_iop_conf_t qe_iop_conf_tab[] = {
31 /* port pin dir open_drain assign */
34 {0, 1, 3, 0, 2}, /* MDIO */
35 {0, 2, 1, 0, 1}, /* MDC */
38 {1, 14, 1, 0, 1}, /* TxD0 */
39 {1, 15, 1, 0, 1}, /* TxD1 */
40 {1, 20, 2, 0, 1}, /* RxD0 */
41 {1, 21, 2, 0, 1}, /* RxD1 */
42 {1, 18, 1, 0, 1}, /* TX_EN */
43 {1, 26, 2, 0, 1}, /* RX_DV */
44 {1, 27, 2, 0, 1}, /* RX_ER */
45 {1, 24, 2, 0, 1}, /* COL */
46 {1, 25, 2, 0, 1}, /* CRS */
47 {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
48 {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
51 {5, 0, 1, 0, 2}, /* UART2_SOUT */
52 {5, 2, 1, 0, 1}, /* UART2_RTS */
53 {5, 3, 2, 0, 2}, /* UART2_SIN */
54 {5, 1, 2, 0, 3}, /* UART2_CTS */
57 {0, 0, 0, 0, QE_IOP_TAB_END},
60 int board_early_init_r (void)
62 void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8);
66 * Because of errata in the UCCs, we have to write to the reserved
67 * registers to slow the clocks down.
75 /* enable the PHY on the PIGGY */
76 setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x10003), 0x01);
83 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
88 msize = CONFIG_SYS_DDR_SIZE;
89 for (ddr_size = msize << 20, ddr_size_log2 = 0;
90 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
95 im->sysconf.ddrlaw[0].ar =
96 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
98 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
99 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
100 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
101 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
102 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
103 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
104 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
105 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
106 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
107 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
108 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
109 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
111 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
116 phys_size_t initdram (int board_type)
118 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
119 extern void ddr_enable_ecc (unsigned int dram_size);
121 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
124 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
127 /* DDR SDRAM - Main SODIMM */
128 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
129 msize = fixed_sdram ();
131 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
133 * Initialize DDR ECC byte
135 ddr_enable_ecc (msize * 1024 * 1024);
138 /* return total bus SDRAM size(bytes) -- DDR */
139 return (msize * 1024 * 1024);
142 int checkboard (void)
144 puts ("Board: Keymile kmeter1\n");
148 #if defined(CONFIG_OF_BOARD_SETUP)
149 void ft_board_setup (void *blob, bd_t *bd)
151 ft_cpu_setup (blob, bd);