2 * (C) Copyright 2013 Keymile AG
3 * Valentin Longchamp <valentin.longchamp@keymile.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include "../common/common.h"
13 /* QRIO GPIO register offsets */
14 #define DIRECT_OFF 0x18
17 int qrio_get_gpio(u8 port_off, u8 gpio_nr)
21 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
23 gprt = in_be32(qrio_base + port_off + GPRT_OFF);
25 return (gprt >> gpio_nr) & 1U;
28 void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value)
32 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
36 gprt = in_be32(qrio_base + port_off + GPRT_OFF);
42 out_be32(qrio_base + port_off + GPRT_OFF, gprt);
45 void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value)
49 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
53 direct = in_be32(qrio_base + port_off + DIRECT_OFF);
55 out_be32(qrio_base + port_off + DIRECT_OFF, direct);
57 qrio_set_gpio(port_off, gpio_nr, value);
60 void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr)
64 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
68 direct = in_be32(qrio_base + port_off + DIRECT_OFF);
70 out_be32(qrio_base + port_off + DIRECT_OFF, direct);
73 void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val)
77 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
81 direct = in_be32(qrio_base + port_off + DIRECT_OFF);
83 /* set to output -> GPIO drives low */
86 /* set to input -> GPIO floating */
89 out_be32(qrio_base + port_off + DIRECT_OFF, direct);
92 #define WDMASK_OFF 0x16
94 void qrio_wdmask(u8 bit, bool wden)
97 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
99 wdmask = in_be16(qrio_base + WDMASK_OFF);
102 wdmask |= (1 << bit);
104 wdmask &= ~(1 << bit);
106 out_be16(qrio_base + WDMASK_OFF, wdmask);
109 #define PRST_OFF 0x1a
111 void qrio_prst(u8 bit, bool en, bool wden)
114 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
116 qrio_wdmask(bit, wden);
118 prst = in_be16(qrio_base + PRST_OFF);
125 out_be16(qrio_base + PRST_OFF, prst);
128 #define PRSTCFG_OFF 0x1c
130 void qrio_prstcfg(u8 bit, u8 mode)
134 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
136 prstcfg = in_be32(qrio_base + PRSTCFG_OFF);
138 for (i = 0; i < 2; i++) {
140 set_bit(2*bit+i, &prstcfg);
142 clear_bit(2*bit+i, &prstcfg);
145 out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
148 #define CTRLH_OFF 0x02
149 #define CTRLH_WRL_BOOT 0x01
150 #define CTRLH_WRL_UNITRUN 0x02
152 void qrio_set_leds(void)
155 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
157 /* set UNIT LED to RED and BOOT LED to ON */
158 ctrlh = in_8(qrio_base + CTRLH_OFF);
159 ctrlh |= (CTRLH_WRL_BOOT | CTRLH_WRL_UNITRUN);
160 out_8(qrio_base + CTRLH_OFF, ctrlh);
163 #define CTRLL_OFF 0x03
164 #define CTRLL_WRB_BUFENA 0x20
166 void qrio_enable_app_buffer(void)
169 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
171 /* enable application buffer */
172 ctrll = in_8(qrio_base + CTRLL_OFF);
173 ctrll |= (CTRLL_WRB_BUFENA);
174 out_8(qrio_base + CTRLL_OFF, ctrll);
177 #define REASON1_OFF 0x12
178 #define REASON1_CPUWD 0x01
180 void qrio_cpuwd_flag(bool flag)
183 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
184 reason1 = in_8(qrio_base + REASON1_OFF);
186 reason1 |= REASON1_CPUWD;
188 reason1 &= ~REASON1_CPUWD;
189 out_8(qrio_base + REASON1_OFF, reason1);
192 #define RSTCFG_OFF 0x11
194 void qrio_uprstreq(u8 mode)
197 void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
199 rstcfg = in_8(qrio_base + RSTCFG_OFF);
201 if (mode & UPREQ_CORE_RST)
202 rstcfg |= UPREQ_CORE_RST;
204 rstcfg &= ~UPREQ_CORE_RST;
206 out_8(qrio_base + RSTCFG_OFF, rstcfg);