2 * (C) Copyright 2000, 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #ifdef CONFIG_KUP4K_LOGO
34 volatile unsigned char *VmemAddr;
35 volatile unsigned char *RegAddr;
38 /* ------------------------------------------------------------------------- */
41 static long int dram_size (long int, long int *, long int);
44 #ifdef CONFIG_KUP4K_LOGO
45 void lcd_logo(bd_t *bd);
48 /* ------------------------------------------------------------------------- */
50 #define _NOT_USED_ 0xFFFFFFFF
52 const uint sdram_table[] =
55 * Single Read. (Offset 0 in UPMA RAM)
57 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
58 0x1FF77C47, /* last */
61 * SDRAM Initialization (offset 5 in UPMA RAM)
63 * This is no UPM entry point. The following definition uses
64 * the remaining space to establish an initialization
65 * sequence, which is executed by a RUN command.
68 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
71 * Burst Read. (Offset 8 in UPMA RAM)
73 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
74 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
75 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
76 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
79 * Single Write. (Offset 18 in UPMA RAM)
81 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
82 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
85 * Burst Write. (Offset 20 in UPMA RAM)
87 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
88 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
90 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
91 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
94 * Refresh (Offset 30 in UPMA RAM)
96 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
97 0xFFFFFC84, 0xFFFFFC07, /* last */
98 _NOT_USED_, _NOT_USED_,
99 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
102 * Exception. (Offset 3c in UPMA RAM)
104 0x7FFFFC07, /* last */
105 _NOT_USED_, _NOT_USED_, _NOT_USED_,
108 /* ------------------------------------------------------------------------- */
112 * Check Board Identity:
115 int checkboard (void)
118 printf ("### No HW ID - assuming KUP4K-Color\n");
122 /* ------------------------------------------------------------------------- */
124 long int initdram (int board_type)
126 volatile immap_t *immap = (immap_t *) CFG_IMMR;
127 volatile memctl8xx_t *memctl = &immap->im_memctl;
128 long int size_b0 = 0;
129 long int size_b1 = 0;
130 long int size_b2 = 0;
132 upmconfig (UPMA, (uint *) sdram_table,
133 sizeof (sdram_table) / sizeof (uint));
136 * Preliminary prescaler for refresh (depends on number of
137 * banks): This value is selected for four cycles every 62.4 us
138 * with two SDRAM banks or four cycles every 31.2 us with one
139 * bank. It will be adjusted after memory sizing.
141 memctl->memc_mptpr = CFG_MPTPR;
143 memctl->memc_mar = 0x00000088;
146 * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
147 * preliminary addresses - these have to be modified after the
148 * SDRAM size has been determined.
150 /* memctl->memc_or1 = CFG_OR1_PRELIM; */
151 /* memctl->memc_br1 = CFG_BR1_PRELIM; */
153 /* memctl->memc_or2 = CFG_OR2_PRELIM; */
154 /* memctl->memc_br2 = CFG_BR2_PRELIM; */
157 memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
161 /* perform SDRAM initializsation sequence */
163 memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
165 memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */
167 memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
170 memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
172 memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */
174 memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
177 memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */
179 memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */
181 memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
184 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
188 size_b0 = 0x00800000;
189 size_b1 = 0x00800000;
190 size_b2 = 0x00800000;
191 memctl->memc_mptpr = CFG_MPTPR;
193 memctl->memc_or1 = 0xFF800A00;
194 memctl->memc_br1 = 0x00000081;
195 memctl->memc_or2 = 0xFF000A00;
196 memctl->memc_br2 = 0x00800081;
197 memctl->memc_or3 = 0xFE000A00;
198 memctl->memc_br3 = 0x01000081;
199 #else /* 3 x 16 MB */
200 size_b0 = 0x01000000;
201 size_b1 = 0x01000000;
202 size_b2 = 0x01000000;
203 memctl->memc_mptpr = CFG_MPTPR;
205 memctl->memc_or1 = 0xFF000A00;
206 memctl->memc_br1 = 0x00000081;
207 memctl->memc_or2 = 0xFE000A00;
208 memctl->memc_br2 = 0x01000081;
209 memctl->memc_or3 = 0xFC000A00;
210 memctl->memc_br3 = 0x02000081;
215 return (size_b0 + size_b1 + size_b2);
218 /* ------------------------------------------------------------------------- */
221 * Check memory range for valid RAM. A simple memory test determines
222 * the actually available RAM size between addresses `base' and
223 * `base + maxsize'. Some (not all) hardware errors are detected:
224 * - short between address lines
225 * - short between data lines
228 static long int dram_size (long int mamr_value, long int *base,
231 volatile immap_t *immap = (immap_t *) CFG_IMMR;
232 volatile memctl8xx_t *memctl = &immap->im_memctl;
233 volatile long int *addr;
235 ulong save[32]; /* to make test non-destructive */
238 memctl->memc_mamr = mamr_value;
240 for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
241 addr = base + cnt; /* pointer arith! */
247 /* write 0 to base address */
252 /* check at base address */
253 if ((val = *addr) != 0) {
258 for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
259 addr = base + cnt; /* pointer arith! */
265 return (cnt * sizeof (long));
272 int misc_init_r (void)
274 DECLARE_GLOBAL_DATA_PTR;
276 #ifdef CONFIG_STATUS_LED
277 volatile immap_t *immap = (immap_t *) CFG_IMMR;
279 #ifdef CONFIG_KUP4K_LOGO
284 #endif /* CONFIG_KUP4K_LOGO */
285 #ifdef CONFIG_IDE_LED
286 /* Configure PA8 as output port */
287 immap->im_ioport.iop_padir |= 0x80;
288 immap->im_ioport.iop_paodr |= 0x80;
289 immap->im_ioport.iop_papar &= ~0x80;
290 immap->im_ioport.iop_padat |= 0x80; /* turn it off */
295 #ifdef CONFIG_KUP4K_LOGO
298 #define PB_LCD_PWM ((uint)0x00004000) /* PB 17 */
300 void lcd_logo (bd_t * bd)
302 FB_INFO_S1D13xxx fb_info;
305 volatile immap_t *immr = (immap_t *) CFG_IMMR;
306 volatile memctl8xx_t *memctl;
310 int r = 8, g = 8, b = 4;
313 immr->im_cpm.cp_pbpar &= ~PB_LCD_PWM;
314 immr->im_cpm.cp_pbodr &= ~PB_LCD_PWM;
315 immr->im_cpm.cp_pbdat &= ~PB_LCD_PWM; /* set to 0 = enabled */
316 immr->im_cpm.cp_pbdir |= PB_LCD_PWM;
319 /*----------------------------------------------------------------------------- */
321 /* Initialize the chip and the frame buffer driver. */
323 /*----------------------------------------------------------------------------- */
324 memctl = &immr->im_memctl;
325 /* memctl->memc_or5 = 0xFFC007F0; / * 4 MB 17 WS or externel TA */
326 /* memctl->memc_br5 = 0x80000801; / * Start at 0x80000000 */
328 memctl->memc_or5 = 0xFFC00708; /* 4 MB 17 WS or externel TA */
329 memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */
335 fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR);
336 fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR);
338 if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28)
339 || (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) {
340 printf ("Warning:LCD Controller S1D13706 not found\n");
344 /* init controller */
345 for (i = 0; i < sizeof (aS1DRegs) / sizeof (aS1DRegs[0]); i++) {
346 s1dReg = aS1DRegs[i].Index;
347 s1dValue = aS1DRegs[i].Value;
348 /* printf("sid1 Index: %02x Register: %02x Wert: %02x\n",i, aS1DRegs[i].Index, aS1DRegs[i].Value); */
349 ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
355 switch (bd->bi_busfreq) {
358 ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
359 ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x28;
362 ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
363 ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x33;
367 ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
368 ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x40;
371 ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
372 ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x4C;
375 printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",
378 ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
379 ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x69;
382 ((S1D_VALUE *) fb_info.RegAddr)[0x10] = 0x00;
384 switch (bd->bi_busfreq) {
387 ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22;
388 ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
391 ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
392 ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
396 ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
397 ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41;
400 ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22;
401 ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
404 printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",
407 ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
408 ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66;
414 /* create and set colormap */
418 for (i = 0; i < 256; i++) {
419 r1 = (rs * ((i / (g * b)) % r)) * 255;
420 g1 = (gs * ((i / b) % g)) * 255;
421 b1 = (bs * ((i) % b)) * 255;
422 /* printf("%d %04x %04x %04x\n",i,r1>>4,g1>>4,b1>>4); */
423 S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4),
428 fb = (char *) (fb_info.VmemAddr);
429 memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240);
431 #endif /* CONFIG_KUP4K_LOGO */
433 #ifdef CONFIG_IDE_LED
434 void ide_led (uchar led, uchar status)
436 volatile immap_t *immap = (immap_t *) CFG_IMMR;
438 /* We have one led for both pcmcia slots */
439 if (status) { /* led on */
440 immap->im_ioport.iop_padat &= ~0x80;
442 immap->im_ioport.iop_padat |= 0x80;