3 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/at91sam9x5_matrix.h>
9 #include <asm/arch/at91sam9_smc.h>
10 #include <asm/arch/at91_common.h>
11 #include <asm/arch/at91_rstc.h>
12 #include <asm/arch/clk.h>
13 #include <asm/arch/gpio.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 /* ------------------------------------------------------------------------- */
21 * Miscelaneous platform dependent initialisations
23 static void wb45n_nand_hw_init(void)
25 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
26 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
29 csa = readl(&matrix->ebicsa);
31 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
32 /* NAND flash on D0 */
33 csa &= ~AT91_MATRIX_NFD0_ON_D16;
34 writel(csa, &matrix->ebicsa);
36 /* Configure SMC CS3 for NAND/SmartMedia */
37 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
38 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
40 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
41 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
43 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
45 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
46 AT91_SMC_MODE_EXNW_DISABLE |
48 AT91_SMC_MODE_TDF_CYCLE(1), &smc->cs[3].mode);
50 at91_periph_clk_enable(ATMEL_ID_PIOCD);
52 /* Configure RDY/BSY */
53 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
54 /* Enable NandFlash */
55 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
56 /* Disable Flash Write Protect Line */
57 at91_set_gpio_output(AT91_PIN_PD10, 1);
59 at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
60 at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
61 at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
62 at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
65 static void wb45n_gpio_hw_init(void)
68 /* Configure wifi gpio CHIP_PWD_L */
69 at91_set_gpio_output(AT91_PIN_PA28, 0);
72 at91_set_gpio_input(AT91_PIN_PB11, 0);
73 at91_set_gpio_output(AT91_PIN_PB12, 0);
75 /* IRQ pin, pullup, deglitch */
76 at91_set_gpio_input(AT91_PIN_PB18, 1);
77 at91_set_gpio_deglitch(AT91_PIN_PB18, 1);
80 int board_eth_init(bd_t *bis)
85 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
90 int board_early_init_f(void)
92 at91_seriald_hw_init();
98 /* address of boot parameters */
99 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
101 wb45n_gpio_hw_init();
103 wb45n_nand_hw_init();
112 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
113 CONFIG_SYS_SDRAM_SIZE);
117 #if defined(CONFIG_SPL_BUILD)
121 void at91_spl_board_init(void)
123 /* Setup GPIO first */
124 wb45n_gpio_hw_init();
127 wb45n_nand_hw_init();
130 void matrix_init(void)
132 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
135 csa = readl(&matrix->ebicsa);
136 /* Pull ups on D0 - D16 */
137 csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
138 csa |= AT91_MATRIX_EBI_DBPD_OFF;
139 /* Normal drive strength */
140 csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
142 csa &= ~AT91_MATRIX_MP_ON;
143 writel(csa, &matrix->ebicsa);
146 #include <asm/arch/atmel_mpddrc.h>
147 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
149 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM);
151 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
152 ATMEL_MPDDRC_CR_NR_ROW_13 |
153 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
154 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
155 ATMEL_MPDDRC_CR_DQMS_SHARED);
159 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
160 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
161 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
162 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
163 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
164 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
165 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
166 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
168 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
169 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
170 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
171 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
173 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
174 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
175 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
176 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
177 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
182 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
183 struct atmel_mpddrc_config ddr2;
188 /* enable DDR2 clock */
189 at91_system_clk_enable(AT91_PMC_DDR);
191 /* Chip select 1 is for DDR2/SDRAM */
192 csa = readl(&matrix->ebicsa);
193 csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
194 writel(csa, &matrix->ebicsa);
196 /* DDRAM2 Controller initialize */
197 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);