2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Torsten Stevens, FHG IMS, stevens@ims.fhg.de
6 * Bruno Achauer, Exet AG, bruno@exet-ag.de.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * Derived from ../tqm8xx/tqm8xx.c
34 /* ------------------------------------------------------------------------- */
36 static long int dram_size (long int, long int *, long int);
38 /* ------------------------------------------------------------------------- */
40 #define _NOT_USED_ 0xFFFFFFFF
42 const uint sdram_table[] =
45 * Single Read. (Offset 0 in UPMA RAM)
47 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
48 0x1ff77c47, /* last */
50 * SDRAM Initialization (offset 5 in UPMA RAM)
52 * This is no UPM entry point. The following definition uses
53 * the remaining space to establish an initialization
54 * sequence, which is executed by a RUN command.
57 0x1ff77c35, 0xefeabc34, 0x1fb57c35, /* last */
59 * Burst Read. (Offset 8 in UPMA RAM)
61 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
62 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */
63 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
64 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
66 * Single Write. (Offset 18 in UPMA RAM)
68 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */
69 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
71 * Burst Write. (Offset 20 in UPMA RAM)
73 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
74 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, /* last */
76 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
77 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
79 * Refresh (Offset 30 in UPMA RAM)
81 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
82 0xfffffc84, 0xfffffc07, 0xfffffc07, /* last */
84 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
86 * Exception. (Offset 3c in UPMA RAM)
88 0x7ffffc07, /* last */
89 _NOT_USED_, _NOT_USED_, _NOT_USED_,
92 /* ------------------------------------------------------------------------- */
96 * Check Board Identity:
98 * Test TQ ID string (TQM8xx...)
99 * If present, check for "L" type (no second DRAM bank),
100 * otherwise "L" type is assumed as default.
102 * Return 1 for "L" type, 0 else.
105 int checkboard (void)
107 printf("Board: Lantec special edition rev.%d\n", CONFIG_LANTEC);
111 /* ------------------------------------------------------------------------- */
113 long int initdram (int board_type)
115 volatile immap_t *immap = (immap_t *)CFG_IMMR;
116 volatile memctl8xx_t *memctl = &immap->im_memctl;
121 * Configure UPMA for SDRAM
123 upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
125 memctl->memc_mptpr = CFG_MPTPR_1BK_8K /* XXX CFG_MPTPR XXX */;
127 /* burst length=4, burst type=sequential, CAS latency=2 */
128 memctl->memc_mar = 0x00000088;
131 * Map controller bank 3 to the SDRAM bank at preliminary address.
133 memctl->memc_or3 = CFG_OR3_PRELIM;
134 memctl->memc_br3 = CFG_BR3_PRELIM;
136 /* initialize memory address register */
137 memctl->memc_mamr = CFG_MAMR_8COL; /* refresh not enabled yet */
139 /* mode initialization (offset 5) */
140 udelay(200); /* 0x80006105 */
141 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x05);
143 /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
144 udelay(1); /* 0x80006130 */
145 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x30);
146 udelay(1); /* 0x80006130 */
147 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x30);
149 udelay(1); /* 0x80006106 */
150 memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x06);
152 memctl->memc_mamr |= MAMR_PTBE; /* refresh enabled */
156 /* Need at least 10 DRAM accesses to stabilize */
157 for (i=0; i<10; ++i) {
158 volatile unsigned long *addr = \
159 (volatile unsigned long *)SDRAM_BASE3_PRELIM;
167 * Check Bank 0 Memory Size for re-configuration
169 size_b0 = dram_size (CFG_MAMR_8COL,
170 (ulong *)SDRAM_BASE3_PRELIM,
173 memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTBE;
179 memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
180 memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
186 /* ------------------------------------------------------------------------- */
189 * Check memory range for valid RAM. A simple memory test determines
190 * the actually available RAM size between addresses `base' and
191 * `base + maxsize'. Some (not all) hardware errors are detected:
192 * - short between address lines
193 * - short between data lines
196 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
198 volatile immap_t *immap = (immap_t *)CFG_IMMR;
199 volatile memctl8xx_t *memctl = &immap->im_memctl;
200 volatile long int *addr;
202 ulong save[32]; /* to make test non-destructive */
205 memctl->memc_mamr = mamr_value;
207 for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
208 addr = base + cnt; /* pointer arith! */
214 /* write 0 to base address */
219 /* check at base address */
220 if ((val = *addr) != 0) {
225 for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
226 addr = base + cnt; /* pointer arith! */
232 return (cnt * sizeof(long));