1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
9 #include <linux/libfdt.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/mx6-ddr.h>
13 #include <asm/arch/mx6-pins.h>
14 #include "asm/arch/crm_regs.h"
15 #include <asm/arch/sys_proto.h>
16 #include <asm/arch/imx-regs.h>
17 #include "asm/arch/iomux.h"
18 #include <asm/mach-imx/iomux-v3.h>
20 #include <environment.h>
21 #include <fsl_esdhc.h>
23 #include <bootcount.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
30 .dram_sdclk_0 = 0x00000030,
31 .dram_sdclk_1 = 0x00000030,
32 .dram_cas = 0x00000030,
33 .dram_ras = 0x00000030,
34 .dram_reset = 0x00000030,
35 .dram_sdcke0 = 0x00003000,
36 .dram_sdcke1 = 0x00003000,
37 .dram_sdba2 = 0x00000000,
38 .dram_sdodt0 = 0x00000030,
39 .dram_sdodt1 = 0x00000030,
41 .dram_sdqs0 = 0x00000030,
42 .dram_sdqs1 = 0x00000030,
43 .dram_sdqs2 = 0x00000030,
44 .dram_sdqs3 = 0x00000030,
45 .dram_sdqs4 = 0x00000030,
46 .dram_sdqs5 = 0x00000030,
47 .dram_sdqs6 = 0x00000030,
48 .dram_sdqs7 = 0x00000030,
50 .dram_dqm0 = 0x00000030,
51 .dram_dqm1 = 0x00000030,
52 .dram_dqm2 = 0x00000030,
53 .dram_dqm3 = 0x00000030,
54 .dram_dqm4 = 0x00000030,
55 .dram_dqm5 = 0x00000030,
56 .dram_dqm6 = 0x00000030,
57 .dram_dqm7 = 0x00000030,
60 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
61 .grp_ddr_type = 0x000c0000,
62 .grp_ddrmode_ctl = 0x00020000,
63 .grp_ddrpke = 0x00000000,
64 .grp_addds = 0x00000030,
65 .grp_ctlds = 0x00000030,
66 .grp_ddrmode = 0x00020000,
67 .grp_b0ds = 0x00000030,
68 .grp_b1ds = 0x00000030,
69 .grp_b2ds = 0x00000030,
70 .grp_b3ds = 0x00000030,
71 .grp_b4ds = 0x00000030,
72 .grp_b5ds = 0x00000030,
73 .grp_b6ds = 0x00000030,
74 .grp_b7ds = 0x00000030,
78 static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
79 .p0_mpwldectrl0 = 0x002D0028,
80 .p0_mpwldectrl1 = 0x0032002D,
81 .p1_mpwldectrl0 = 0x00210036,
82 .p1_mpwldectrl1 = 0x0019002E,
83 .p0_mpdgctrl0 = 0x4349035C,
84 .p0_mpdgctrl1 = 0x0348033D,
85 .p1_mpdgctrl0 = 0x43550362,
86 .p1_mpdgctrl1 = 0x03520316,
87 .p0_mprddlctl = 0x41393940,
88 .p1_mprddlctl = 0x3F3A3C47,
89 .p0_mpwrdlctl = 0x413A423A,
90 .p1_mpwrdlctl = 0x4042483E,
93 /* MT41K128M16JT-125 (2Gb density) */
94 static const struct mx6_ddr3_cfg mt41k128m16jt_125 = {
107 static void ccgr_init(void)
109 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
111 writel(0x00C03F3F, &ccm->CCGR0);
112 writel(0x0030FC3F, &ccm->CCGR1);
113 writel(0x0FFFCFC0, &ccm->CCGR2);
114 writel(0x3FF00000, &ccm->CCGR3);
115 writel(0x00FFF300, &ccm->CCGR4);
116 writel(0x0F0000C3, &ccm->CCGR5);
117 writel(0x000003FF, &ccm->CCGR6);
120 static void spl_dram_init(void)
122 struct mx6_ddr_sysinfo sysinfo = {
123 /* width of data bus:0=16,1=32,2=64 */
125 /* config for full 4GB range so that get_mem_size() works */
126 .cs_density = 32, /* 32Gb per CS */
127 /* single chip select */
130 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
131 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
132 .walat = 1, /* Write additional latency */
133 .ralat = 5, /* Read additional latency */
134 .mif3_mode = 3, /* Command prediction working mode */
135 .bi_on = 1, /* Bank interleaving enabled */
136 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
137 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
138 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
139 .ddr_type = DDR_TYPE_DDR3,
140 .refsel = 1, /* Refresh cycles at 32KHz */
141 .refr = 7, /* 8 refresh commands per refresh cycle */
144 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
145 mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);
148 #ifdef CONFIG_SPL_SPI_SUPPORT
149 static void displ5_init_ecspi(void)
151 displ5_set_iomux_ecspi_spl();
152 enable_spi_clk(1, 1);
155 static inline void displ5_init_ecspi(void) { }
158 #ifdef CONFIG_SPL_MMC_SUPPORT
159 static struct fsl_esdhc_cfg usdhc_cfg = {
160 .esdhc_base = USDHC4_BASE_ADDR,
164 int board_mmc_init(bd_t *bd)
166 displ5_set_iomux_usdhc_spl();
168 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
169 gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
171 return fsl_esdhc_initialize(bd, &usdhc_cfg);
175 void board_init_f(ulong dummy)
186 displ5_set_iomux_uart_spl();
188 /* UART clocks enabled and gd valid - init serial console */
189 preloader_console_init();
193 /* DDR initialization */
197 memset(__bss_start, 0, __bss_end - __bss_start);
199 displ5_set_iomux_misc_spl();
201 /* Initialize and reset WDT in SPL */
205 /* load/boot image from boot device */
206 board_init_r(NULL, 0);
209 #define EM_PAD IMX_GPIO_NR(3, 29)
210 int board_check_emergency_pad(void)
214 ret = gpio_direction_input(EM_PAD);
218 return !gpio_get_value(EM_PAD);
221 void board_boot_order(u32 *spl_boot_list)
223 /* Default boot sequence SPI -> MMC */
224 spl_boot_list[0] = spl_boot_device();
225 spl_boot_list[1] = BOOT_DEVICE_MMC1;
226 spl_boot_list[2] = BOOT_DEVICE_UART;
227 spl_boot_list[3] = BOOT_DEVICE_NONE;
230 * In case of emergency PAD pressed, we always boot
231 * to proper u-boot and perform recovery tasks there.
233 if (board_check_emergency_pad())
236 #ifdef CONFIG_SPL_ENV_SUPPORT
240 if (env_init() || env_load())
243 s = env_get("BOOT_FROM");
244 if (s && !bootcount_error() && strcmp(s, "ACTIVE") == 0) {
245 spl_boot_list[0] = BOOT_DEVICE_MMC1;
246 spl_boot_list[1] = spl_boot_device();
251 void reset_cpu(ulong addr) {}
253 #ifdef CONFIG_SPL_LOAD_FIT
254 int board_fit_config_name_match(const char *name)
260 #ifdef CONFIG_SPL_OS_BOOT
261 /* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */
262 int spl_start_uboot(void)
264 /* break into full u-boot on 'c' */
265 if (serial_tstc() && serial_getc() == 'c')
268 #ifdef CONFIG_SPL_ENV_SUPPORT
269 if (env_get_yesno("boot_os") != 1)