2 * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
3 * Applications Processor Reference Manual, Rev. 0.2".
5 * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
6 * (C) Copyright 2009 Ilya Yanok <yanok@emcraft.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/macro.h>
28 #include <asm/arch/imx-regs.h>
29 #include <asm/arch/asm-offsets.h>
31 SOC_ESDCTL_BASE_W: .word IMX_ESD_BASE
32 SOC_SI_ID_REG_W: .word IMX_SYSTEM_CTL_BASE
33 SDRAM_ESDCFG_T1_W: .word SDRAM_ESDCFG_REGISTER_VAL(0)
34 SDRAM_ESDCFG_T2_W: .word SDRAM_ESDCFG_REGISTER_VAL(3)
35 SDRAM_PRECHARGE_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_PRECHARGE | \
36 ESDCTL_ROW13 | ESDCTL_COL10)
37 SDRAM_AUTOREF_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_AUTO_REF | \
38 ESDCTL_ROW13 | ESDCTL_COL10)
39 SDRAM_LOADMODE_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_LOAD_MODE | \
40 ESDCTL_ROW13 | ESDCTL_COL10)
41 SDRAM_NORMAL_CMD_W: .word SDRAM_ESDCTL_REGISTER_VAL
45 * setup AIPI1 and AIPI2
47 write32 AIPI1_PSR0, AIPI1_PSR0_VAL
48 write32 AIPI1_PSR1, AIPI1_PSR1_VAL
49 write32 AIPI2_PSR0, AIPI2_PSR0_VAL
50 write32 AIPI2_PSR1, AIPI2_PSR1_VAL
56 /* disable MPLL/SPLL first */
58 bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
61 write32 MPCTL0, MPCTL0_VAL
62 write32 SPCTL0, SPCTL0_VAL
64 write32 CSCR, CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART
71 /* peripheral clock divider */
72 write32 PCDR0, PCDR0_VAL
73 write32 PCDR1, PCDR1_VAL
75 /* Configure PCCR0 and PCCR1 */
76 write32 PCCR0, PCCR0_VAL
77 write32 PCCR1, PCCR1_VAL
79 .endm /* init_clock */
82 ldr r0, SOC_ESDCTL_BASE_W
85 /* Do initial reset */
86 mov r1, #ESDMISC_MDDR_DL_RST
87 str r1, [r0, #ESDMISC_ROF]
89 /* Hold for more than 200ns */
92 /* Activate LPDDR iface */
93 mov r1, #ESDMISC_MDDREN
94 str r1, [r0, #ESDMISC_ROF]
96 /* Check The chip version TO1 or TO2 */
97 ldr r1, SOC_SI_ID_REG_W
99 ands r1, r1, #0xF0000000
100 /* add Latency on CAS only for TO2 */
101 ldreq r1, SDRAM_ESDCFG_T2_W
102 ldrne r1, SDRAM_ESDCFG_T1_W
103 str r1, [r0, #ESDCFG0_ROF]
105 /* Run initialization sequence */
106 ldr r1, SDRAM_PRECHARGE_CMD_W
107 str r1, [r0, #ESDCTL0_ROF]
108 ldr r1, [r2, #SDRAM_ALL_VAL]
110 ldr r1, SDRAM_AUTOREF_CMD_W
111 str r1, [r0, #ESDCTL0_ROF]
112 ldr r1, [r2, #SDRAM_ALL_VAL]
113 ldr r1, [r2, #SDRAM_ALL_VAL]
115 ldr r1, SDRAM_LOADMODE_CMD_W
116 str r1, [r0, #ESDCTL0_ROF]
117 ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
118 add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
121 ldr r1, SDRAM_NORMAL_CMD_W
122 str r1, [r0, #ESDCTL0_ROF]
124 #if (CONFIG_NR_DRAM_BANKS > 1)
126 mov r2, #PHYS_SDRAM_2
128 /* Check The chip version TO1 or TO2 */
129 ldr r1, SOC_SI_ID_REG_W
131 ands r1, r1, #0xF0000000
132 /* add Latency on CAS only for TO2 */
133 ldreq r1, SDRAM_ESDCFG_T2_W
134 ldrne r1, SDRAM_ESDCFG_T1_W
135 str r1, [r0, #ESDCFG1_ROF]
137 /* Run initialization sequence */
138 ldr r1, SDRAM_PRECHARGE_CMD_W
139 str r1, [r0, #ESDCTL1_ROF]
140 ldr r1, [r2, #SDRAM_ALL_VAL]
142 ldr r1, SDRAM_AUTOREF_CMD_W
143 str r1, [r0, #ESDCTL1_ROF]
144 ldr r1, [r2, #SDRAM_ALL_VAL]
145 ldr r1, [r2, #SDRAM_ALL_VAL]
147 ldr r1, SDRAM_LOADMODE_CMD_W
148 str r1, [r0, #ESDCTL1_ROF]
149 ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
150 add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
153 ldr r1, SDRAM_NORMAL_CMD_W
154 str r1, [r0, #ESDCTL1_ROF]
155 #endif /* CONFIG_NR_DRAM_BANKS > 1 */
157 .endm /* sdram_init */