2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
12 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
14 * SPDX-License-Identifier: GPL-2.0+
18 #include <fdt_support.h>
22 #include <asm/processor.h>
25 #ifndef CONFIG_SYS_RAMBOOT
26 static void sdram_start (int hi_addr)
28 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
30 /* unlock mode register */
31 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
32 (SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
33 __asm__ volatile ("sync");
35 /* precharge all banks */
36 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
37 (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
38 __asm__ volatile ("sync");
41 /* set mode register: extended mode */
42 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE, (SDRAM_EMODE));
43 __asm__ volatile ("sync");
45 /* set mode register: reset DLL */
46 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE,
47 (SDRAM_MODE | 0x04000000));
48 __asm__ volatile ("sync");
51 /* precharge all banks */
52 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
53 (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
54 __asm__ volatile ("sync");
57 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
58 (SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
59 __asm__ volatile ("sync");
61 /* set mode register */
62 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_MODE, (SDRAM_MODE));
63 __asm__ volatile ("sync");
65 /* normal operation */
66 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CTRL,
67 (SDRAM_CONTROL | hi_addr_bit));
68 __asm__ volatile ("sync");
73 * ATTENTION: Although partially referenced initdram does NOT make real use
74 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
75 * is something else than 0x00000000.
78 phys_size_t initdram (int board_type)
84 #ifndef CONFIG_SYS_RAMBOOT
87 /* setup SDRAM chip selects */
88 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG, 0x0000001c); /* 512MB at 0x0 */
89 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, 0x80000000);/* disabled */
90 __asm__ volatile ("sync");
92 /* setup config registers */
93 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
94 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
95 __asm__ volatile ("sync");
99 out_be32 ((unsigned __iomem *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
100 __asm__ volatile ("sync");
103 /* find RAM size using SDRAM CS0 only */
105 test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
107 test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
115 /* memory smaller than 1MB is impossible */
116 if (dramsize < (1 << 20)) {
120 /* set SDRAM CS0 size according to the amount of RAM found */
122 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG,
123 (0x13 + __builtin_ffs(dramsize >> 20) - 1));
125 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
128 /* let SDRAM CS1 start right after CS0 */
129 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, (dramsize + 0x0000001c));/*512MB*/
131 /* find RAM size using SDRAM CS1 only */
134 test2 = test1 = get_ram_size ((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
137 test2 = get_ram_size ((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
146 /* memory smaller than 1MB is impossible */
147 if (dramsize2 < (1 << 20)) {
151 /* set SDRAM CS1 size according to the amount of RAM found */
153 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG,
154 (dramsize | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
156 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
159 #else /* CONFIG_SYS_RAMBOOT */
161 /* retrieve size of memory connected to SDRAM CS0 */
162 dramsize = in_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
163 if (dramsize >= 0x13) {
164 dramsize = (1 << (dramsize - 0x13)) << 20;
169 /* retrieve size of memory connected to SDRAM CS1 */
170 dramsize2 = in_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
171 if (dramsize2 >= 0x13) {
172 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
177 #endif /* CONFIG_SYS_RAMBOOT */
180 * On MPC5200B we need to set the special configuration delay in the
181 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
182 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
184 * "The SDelay should be written to a value of 0x00000004. It is
185 * required to account for changes caused by normal wafer processing
190 if ((SVR_MJREV(svr) >= 2) &&
191 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
193 out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_SDELAY, 0x04);
194 __asm__ volatile ("sync");
197 return dramsize + dramsize2;
200 int checkboard (void)
202 puts ("Board: MUC.MC-52 HW WDT ");
203 #if defined(CONFIG_HW_WATCHDOG)
211 #ifdef CONFIG_PREBOOT
213 static uchar kbd_magic_prefix[] = "key_magic";
214 static uchar kbd_command_prefix[] = "key_cmd";
225 struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
227 kbd_data->s1 = in_8 ((volatile uchar*)CONFIG_SYS_STATUS1_BASE);
228 kbd_data->s2 = in_8 ((volatile uchar*)CONFIG_SYS_STATUS2_BASE);
233 static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
238 if (s1 >= '0' && s1 <= '9')
240 else if (s1 >= 'a' && s1 <= 'f')
242 else if (s1 >= 'A' && s1 <= 'F')
247 if (((S1_ROT & kbd_data->s1) >> 4) != s1)
250 s2 = (S2_Q | S2_M) & kbd_data->s2;
264 if (s2 == (S2_Q | S2_M))
276 static char *key_match (const struct kbd_data_t *kbd_data)
278 char magic[sizeof (kbd_magic_prefix) + 1];
280 char *kbd_magic_keys;
283 * The following string defines the characters that can be appended
284 * to "key_magic" to form the names of environment variables that
285 * hold "magic" key codes, i. e. such key codes that can cause
286 * pre-boot actions. If the string is empty (""), then only
287 * "key_magic" is checked (old behaviour); the string "125" causes
288 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
290 if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
293 /* loop over all magic keys;
294 * use '\0' suffix in case of empty string
296 for (suffix = kbd_magic_keys; *suffix ||
297 suffix == kbd_magic_keys; ++suffix) {
298 sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
300 if (compare_magic(kbd_data, getenv(magic)) == 0) {
301 char cmd_name[sizeof (kbd_command_prefix) + 1];
304 sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
305 cmd = getenv (cmd_name);
314 #endif /* CONFIG_PREBOOT */
316 int misc_init_r (void)
318 #ifdef CONFIG_PREBOOT
319 struct kbd_data_t kbd_data;
321 char *str = strdup (key_match (get_keys (&kbd_data)));
322 /* Set or delete definition */
323 setenv ("preboot", str);
325 #endif /* CONFIG_PREBOOT */
327 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x38), ' ');
328 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x39), ' ');
329 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3A), ' ');
330 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3B), ' ');
331 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3C), ' ');
332 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3D), ' ');
333 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3E), ' ');
334 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3F), ' ');
339 int board_early_init_r (void)
341 out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_CFG, in_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_CFG) & ~0x1);
342 out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_FLASH_BASE));
343 out_be32 ((unsigned __iomem *)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_FLASH_BASE));
344 out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_STOP,
345 STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE));
346 out_be32 ((unsigned __iomem *)MPC5XXX_CS0_STOP,
347 STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE));
351 int last_stage_init (void)
353 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x38), 'M');
354 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x39), 'U');
355 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3A), 'C');
356 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3B), '.');
357 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3C), 'M');
358 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3D), 'C');
359 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3E), '5');
360 out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3F), '2');
365 #if defined(CONFIG_HW_WATCHDOG)
366 #define GPT_OUT_0 0x00000027
367 #define GPT_OUT_1 0x00000037
368 void hw_watchdog_reset (void)
370 /* Trigger HW Watchdog with TIMER_0 */
371 out_be32 ((unsigned __iomem *)MPC5XXX_GPT0_ENABLE, GPT_OUT_1);
372 out_be32 ((unsigned __iomem *)MPC5XXX_GPT0_ENABLE, GPT_OUT_0);
377 static struct pci_controller hose;
379 extern void pci_mpc5xxx_init (struct pci_controller *);
381 void pci_init_board (void)
383 pci_mpc5xxx_init (&hose);
387 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
388 int ft_board_setup(void *blob, bd_t *bd)
390 ft_cpu_setup(blob, bd);
394 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */