3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2005-2007
9 * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <environment.h>
37 #include <fdt_support.h>
43 #define SDRAM_MODE 0x00CD0000
44 #define SDRAM_CONTROL 0x504F0000
45 #define SDRAM_CONFIG1 0xD2322800
46 #define SDRAM_CONFIG2 0x8AD70000
48 DECLARE_GLOBAL_DATA_PTR;
50 static void sdram_start (int hi_addr)
52 long hi_bit = hi_addr ? 0x01000000 : 0;
54 /* unlock mode register */
55 out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | hi_bit);
57 /* precharge all banks */
58 out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
60 /* precharge all banks */
61 out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
64 out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | hi_bit);
66 /* set mode register */
67 out_be32((u32*)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
69 /* normal operation */
70 out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
73 phys_addr_t initdram (int board_type)
79 /* setup SDRAM chip selects */
80 out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
82 /* setup config registers */
83 out_be32((u32*)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
84 out_be32((u32*)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
86 /* find RAM size using SDRAM CS0 only */
88 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
90 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
97 if (dramsize < (1 << 20))
101 out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x13 +
102 __builtin_ffs(dramsize >> 20) - 1);
104 out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0);
109 void mvbc_init_gpio(void)
111 struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
113 printf("Ports : 0x%08x\n", gpio->port_config);
114 printf("PORCFG: 0x%08lx\n", *(vu_long*)MPC5XXX_CDM_PORCFG);
116 out_be32(&gpio->simple_ddr, SIMPLE_DDR);
117 out_be32(&gpio->simple_dvo, SIMPLE_DVO);
118 out_be32(&gpio->simple_ode, SIMPLE_ODE);
119 out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
121 out_8(&gpio->sint_ode, SINT_ODE);
122 out_8(&gpio->sint_ddr, SINT_DDR);
123 out_8(&gpio->sint_dvo, SINT_DVO);
124 out_8(&gpio->sint_inten, SINT_INTEN);
125 out_be16(&gpio->sint_itype, SINT_ITYPE);
126 out_8(&gpio->sint_gpioe, SINT_GPIOEN);
128 out_8((u8*)MPC5XXX_WU_GPIO_ODE, WKUP_ODE);
129 out_8((u8*)MPC5XXX_WU_GPIO_DIR, WKUP_DIR);
130 out_8((u8*)MPC5XXX_WU_GPIO_DATA_O, WKUP_DO);
131 out_8((u8*)MPC5XXX_WU_GPIO_ENABLE, WKUP_EN);
133 printf("simple_gpioe: 0x%08x\n", gpio->simple_gpioe);
134 printf("sint_gpioe : 0x%08x\n", gpio->sint_gpioe);
137 void reset_environment(void)
141 printf("\n*** RESET ENVIRONMENT ***\n");
142 memset(sernr, 0, sizeof(sernr));
143 s = getenv("serial#");
145 printf("found serial# : %s\n", s);
146 strncpy(sernr, s, 64);
151 setenv("serial#", sernr);
154 int misc_init_r(void)
156 char *s = getenv("reset_env");
159 if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
162 if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
165 if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
168 printf(" === FACTORY RESET ===\n");
178 printf("Board: Matrix Vision mvBlueCOUGAR-P\n");
183 void flash_preinit(void)
186 * Now, when we are in RAM, enable flash write
187 * access for detection process.
188 * Note that CS_BOOT cannot be cleared when
189 * executing in flash.
191 clrbits_be32((u32*)MPC5XXX_BOOTCS_CFG, 0x1);
194 void flash_afterinit(ulong size)
196 out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_BOOTCS_START |
198 out_be32((u32*)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_BOOTCS_START |
200 out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
202 out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
206 void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
208 unsigned char line = 0xff;
211 if (PCI_BUS(dev) == 0) {
212 switch (PCI_DEV (dev)) {
215 pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base);
216 printf("found FPA - enable arbitration\n");
217 writel(0x03, (u32*)(base + 0x80c0));
218 writel(0xf0, (u32*)(base + 0x8080));
226 printf ("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV (dev));
229 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line);
233 struct pci_controller hose = {
234 fixup_irq:pci_mvbc_fixup_irq
237 int mvbc_p_load_fpga(void)
239 size_t data_size = 0;
240 void *fpga_data = NULL;
241 char *datastr = getenv("fpgadata");
242 char *sizestr = getenv("fpgadatasize");
245 fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
247 data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
249 return fpga_load(0, fpga_data, data_size);
252 extern void pci_mpc5xxx_init(struct pci_controller *);
254 void pci_init_board(void)
260 s = getenv("skip_fpga");
262 printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
266 printf("loading FPGA ... ");
270 pci_mpc5xxx_init(&hose);
273 u8 *dhcp_vendorex_prep(u8 *e)
277 /* DHCP vendor-class-identifier = 60 */
278 if ((ptr = getenv("dhcp_vendor-class-identifier"))) {
284 /* DHCP_CLIENT_IDENTIFIER = 61 */
285 if ((ptr = getenv("dhcp_client_id"))) {
295 u8 *dhcp_vendorex_proc (u8 *popt)
300 void show_boot_progress(int val)
302 struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
305 case 0: /* FPGA ok */
306 setbits_be32(&gpio->simple_dvo, 0x80);
309 setbits_be32(&gpio->simple_dvo, 0x40);
312 setbits_be32(&gpio->simple_dvo, 0x20);
315 setbits_be32(&gpio->simple_dvo, 0x10);
323 void ft_board_setup(void *blob, bd_t *bd)
325 ft_cpu_setup(blob, bd);
326 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
329 int board_eth_init(bd_t *bis)
331 cpu_eth_init(bis); /* Built in FEC comes first */
332 return pci_eth_init(bis);