2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
5 * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/mpc8349_pci.h>
33 #if defined(CONFIG_OF_LIBFDT)
37 #include "../common/mv_common.h"
42 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
46 char *s = getenv("ddr_size");
48 msize = CONFIG_SYS_DDR_SIZE;
50 u32 env_ddr_size = simple_strtoul(s, NULL, 10);
51 if (env_ddr_size == 512)
55 for (ddr_size = msize << 20, ddr_size_log2 = 0;
57 ddr_size = ddr_size >> 1, ddr_size_log2++) {
61 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
62 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
65 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
66 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
67 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
68 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
69 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
70 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
71 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
72 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
73 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
74 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
75 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
76 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
81 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
89 phys_size_t initdram(int board_type)
91 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
94 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
97 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
98 msize = fixed_sdram();
100 /* return total bus RAM size(bytes) */
101 return msize * 1024 * 1024;
104 int misc_init_r(void)
106 char *s = getenv("reset_env");
109 mv_reset_environment();
117 puts("Board: Matrix Vision mvBlueLYNX-M7\n");
122 #ifdef CONFIG_HARD_SPI
123 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
125 return bus == 0 && cs == 0;
128 void spi_cs_activate(struct spi_slave *slave)
130 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
132 iopd->dat &= ~MVBLM7_MMC_CS;
135 void spi_cs_deactivate(struct spi_slave *slave)
137 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
139 iopd->dat |= ~MVBLM7_MMC_CS;
143 #if defined(CONFIG_OF_BOARD_SETUP)
144 void ft_board_setup(void *blob, bd_t *bd)
146 ft_cpu_setup(blob, bd);
148 ft_pci_setup(blob, bd);