2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
5 * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #if defined(CONFIG_OF_LIBFDT)
35 #include "../common/mv_common.h"
37 DECLARE_GLOBAL_DATA_PTR;
39 static struct pci_region pci_regions[] = {
41 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
42 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
43 size: CONFIG_SYS_PCI1_MEM_SIZE,
44 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
47 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
48 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
49 size: CONFIG_SYS_PCI1_MMIO_SIZE,
53 bus_start: CONFIG_SYS_PCI1_IO_BASE,
54 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
55 size: CONFIG_SYS_PCI1_IO_SIZE,
60 void pci_init_board(void)
63 volatile immap_t *immr;
64 volatile pcictrl83xx_t *pci_ctrl;
65 volatile gpio83xx_t *gpio;
66 volatile clk83xx_t *clk;
67 volatile law83xx_t *pci_law;
68 struct pci_region *reg[] = { pci_regions };
70 immr = (immap_t *) CONFIG_SYS_IMMR;
71 clk = (clk83xx_t *) &immr->clk;
72 pci_ctrl = immr->pci_ctrl;
73 pci_law = immr->sysconf.pcilaw;
74 gpio = (volatile gpio83xx_t *)&immr->gpio[0];
76 gpio->dat = MV_GPIO_DAT;
77 gpio->odr = MV_GPIO_ODE;
78 gpio->dir = MV_GPIO_OUT;
80 printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
86 gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK);
88 /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */
89 clk->occr = 0xc0000000;
95 for (i = 0; i < 1000; ++i)
98 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
99 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB;
101 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
102 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
104 mpc83xx_pci_init(1, reg);