2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
5 * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
7 * SPDX-License-Identifier: GPL-2.0+
11 #if defined(CONFIG_OF_LIBFDT)
19 #include "../common/mv_common.h"
21 DECLARE_GLOBAL_DATA_PTR;
23 static struct pci_region pci_regions[] = {
25 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
26 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
27 size: CONFIG_SYS_PCI1_MEM_SIZE,
28 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
31 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
32 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
33 size: CONFIG_SYS_PCI1_MMIO_SIZE,
37 bus_start: CONFIG_SYS_PCI1_IO_BASE,
38 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
39 size: CONFIG_SYS_PCI1_IO_SIZE,
44 void pci_init_board(void)
47 volatile immap_t *immr;
48 volatile pcictrl83xx_t *pci_ctrl;
49 volatile gpio83xx_t *gpio;
50 volatile clk83xx_t *clk;
51 volatile law83xx_t *pci_law;
52 struct pci_region *reg[] = { pci_regions };
54 immr = (immap_t *) CONFIG_SYS_IMMR;
55 clk = (clk83xx_t *) &immr->clk;
56 pci_ctrl = immr->pci_ctrl;
57 pci_law = immr->sysconf.pcilaw;
58 gpio = (volatile gpio83xx_t *)&immr->gpio[0];
60 gpio->dat = MV_GPIO_DAT;
61 gpio->odr = MV_GPIO_ODE;
62 gpio->dir = MV_GPIO_OUT;
64 printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
70 gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK);
72 /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */
73 clk->occr = 0xc0000000;
79 for (i = 0; i < 1000; ++i)
82 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
83 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB;
85 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
86 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
88 mpc83xx_pci_init(1, reg);