3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2005-2010
9 * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <environment.h>
41 #include "../common/mv_common.h"
44 #define SDRAM_MODE 0x018D0000
45 #define SDRAM_EMODE 0x40090000
46 #define SDRAM_CONTROL 0x715f0f00
47 #define SDRAM_CONFIG1 0xd3722930
48 #define SDRAM_CONFIG2 0x46770000
50 DECLARE_GLOBAL_DATA_PTR;
52 static void sdram_start(int hi_addr)
54 long hi_bit = hi_addr ? 0x01000000 : 0;
56 /* unlock mode register */
57 out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 |
60 /* precharge all banks */
61 out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
64 /* set mode register: extended mode */
65 out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
67 /* set mode register: reset DLL */
68 out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
70 /* precharge all banks */
71 out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
75 out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 |
78 /* set mode register */
79 out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
81 /* normal operation */
82 out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
85 phys_addr_t initdram(int board_type)
91 /* setup SDRAM chip selects */
92 out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
94 /* setup config registers */
95 out_be32((u32 *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
96 out_be32((u32 *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
98 /* find RAM size using SDRAM CS0 only */
100 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
102 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
109 if (dramsize < (1 << 20))
113 out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x13 +
114 __builtin_ffs(dramsize >> 20) - 1);
116 out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0);
121 void mvsmr_init_gpio(void)
123 struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
124 struct mpc5xxx_wu_gpio *wu_gpio =
125 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
126 struct mpc5xxx_gpt_0_7 *timers = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
128 printf("Ports : 0x%08x\n", gpio->port_config);
129 printf("PORCFG: 0x%08x\n", in_be32((unsigned *)MPC5XXX_CDM_PORCFG));
131 out_be32(&gpio->simple_ddr, SIMPLE_DDR);
132 out_be32(&gpio->simple_dvo, SIMPLE_DVO);
133 out_be32(&gpio->simple_ode, SIMPLE_ODE);
134 out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
136 out_8(&gpio->sint_ode, SINT_ODE);
137 out_8(&gpio->sint_ddr, SINT_DDR);
138 out_8(&gpio->sint_dvo, SINT_DVO);
139 out_8(&gpio->sint_inten, SINT_INTEN);
140 out_be16(&gpio->sint_itype, SINT_ITYPE);
141 out_8(&gpio->sint_gpioe, SINT_GPIOEN);
143 out_8(&wu_gpio->ode, WKUP_ODE);
144 out_8(&wu_gpio->ddr, WKUP_DIR);
145 out_8(&wu_gpio->dvo, WKUP_DO);
146 out_8(&wu_gpio->enable, WKUP_EN);
148 out_be32(&timers->gpt0.emsr, 0x00000234); /* OD output high */
149 out_be32(&timers->gpt1.emsr, 0x00000234);
150 out_be32(&timers->gpt2.emsr, 0x00000234);
151 out_be32(&timers->gpt3.emsr, 0x00000234);
152 out_be32(&timers->gpt4.emsr, 0x00000234);
153 out_be32(&timers->gpt5.emsr, 0x00000234);
154 out_be32(&timers->gpt6.emsr, 0x00000024); /* push-pull output low */
155 out_be32(&timers->gpt7.emsr, 0x00000024);
158 int misc_init_r(void)
160 char *s = getenv("reset_env");
163 printf(" === FACTORY RESET ===\n");
164 mv_reset_environment();
171 void mvsmr_get_dbg_present(void)
173 struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
174 struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
176 if (in_be32(&gpio->simple_ival) & COP_PRESENT) {
177 setenv("dbg_present", "no\0");
178 setenv("bootstopkey", "abcdefghijklmnopqrstuvwxyz\0");
180 setenv("dbg_present", "yes\0");
181 setenv("bootstopkey", "s\0");
182 setbits_8(&psc->command, PSC_RX_ENABLE);
186 void mvsmr_get_service_mode(void)
188 struct mpc5xxx_wu_gpio *wu_gpio =
189 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
191 if (in_8(&wu_gpio->ival) & SERVICE_MODE)
192 setenv("servicemode", "no\0");
194 setenv("servicemode", "yes\0");
197 int mvsmr_get_mac(void)
199 unsigned char mac[6];
200 struct mpc5xxx_wu_gpio *wu_gpio =
201 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
203 if (in_8(&wu_gpio->ival) & LAN_PRSNT) {
204 setenv("lan_present", "no\0");
207 setenv("lan_present", "yes\0");
209 i2c_read(0x50, 0, 1, mac, 6);
211 eth_setenv_enetaddr("ethaddr", mac);
219 printf("Board: Matrix Vision mvSMR\n");
224 void flash_preinit(void)
227 * Now, when we are in RAM, enable flash write
228 * access for detection process.
229 * Note that CS_BOOT cannot be cleared when
230 * executing in flash.
232 clrbits_be32((u32 *)MPC5XXX_BOOTCS_CFG, 0x1);
235 void flash_afterinit(ulong size)
237 out_be32((u32 *)MPC5XXX_BOOTCS_START,
238 START_REG(CONFIG_SYS_BOOTCS_START | size));
239 out_be32((u32 *)MPC5XXX_CS0_START,
240 START_REG(CONFIG_SYS_BOOTCS_START | size));
241 out_be32((u32 *)MPC5XXX_BOOTCS_STOP,
242 STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
243 out_be32((u32 *)MPC5XXX_CS0_STOP,
244 STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
247 struct pci_controller hose;
249 void pci_init_board(void)
251 mvsmr_get_dbg_present();
252 mvsmr_get_service_mode();
255 pci_mpc5xxx_init(&hose);
258 int board_eth_init(bd_t *bis)
260 if (!mvsmr_get_mac())
261 return cpu_eth_init(bis);
263 return pci_eth_init(bis);