2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/processor.h>
16 /* Two MT48LC8M32B2 for 32 MB */
17 /* #include "mt48lc8m32b2-6-7.h" */
19 /* One MT48LC16M32S2 for 64 MB */
20 /* #include "mt48lc16m32s2-75.h" */
21 #if defined (CONFIG_MCC200_SDRAM)
22 #include "mt48lc16m16a2-75.h"
24 #include "mt46v16m16-75.h"
27 DECLARE_GLOBAL_DATA_PTR;
29 extern flash_info_t flash_info[]; /* FLASH chips info */
31 extern int do_auto_update(void);
32 ulong flash_get_size (ulong base, int banknum);
34 #ifndef CONFIG_SYS_RAMBOOT
35 static void sdram_start (int hi_addr)
37 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
39 /* unlock mode register */
40 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
41 __asm__ volatile ("sync");
43 /* precharge all banks */
44 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
45 __asm__ volatile ("sync");
48 /* set mode register: extended mode */
49 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
50 __asm__ volatile ("sync");
52 /* set mode register: reset DLL */
53 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
54 __asm__ volatile ("sync");
57 /* precharge all banks */
58 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
59 __asm__ volatile ("sync");
62 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
63 __asm__ volatile ("sync");
65 /* set mode register */
66 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
67 __asm__ volatile ("sync");
69 /* normal operation */
70 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
71 __asm__ volatile ("sync");
78 * ATTENTION: Although partially referenced initdram does NOT make real use
79 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
80 * is something else than 0x00000000.
83 phys_size_t initdram (int board_type)
88 #ifndef CONFIG_SYS_RAMBOOT
91 /* setup SDRAM chip selects */
92 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
93 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
94 __asm__ volatile ("sync");
96 /* setup config registers */
97 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
98 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
99 __asm__ volatile ("sync");
103 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
104 __asm__ volatile ("sync");
107 /* find RAM size using SDRAM CS0 only */
109 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
111 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
119 /* memory smaller than 1MB is impossible */
120 if (dramsize < (1 << 20)) {
124 /* set SDRAM CS0 size according to the amount of RAM found */
126 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
128 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
131 /* let SDRAM CS1 start right after CS0 */
132 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
134 /* find RAM size using SDRAM CS1 only */
137 test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
140 test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
149 /* memory smaller than 1MB is impossible */
150 if (dramsize2 < (1 << 20)) {
154 /* set SDRAM CS1 size according to the amount of RAM found */
156 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
157 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
159 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
162 #else /* CONFIG_SYS_RAMBOOT */
164 /* retrieve size of memory connected to SDRAM CS0 */
165 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
166 if (dramsize >= 0x13) {
167 dramsize = (1 << (dramsize - 0x13)) << 20;
172 /* retrieve size of memory connected to SDRAM CS1 */
173 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
174 if (dramsize2 >= 0x13) {
175 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
180 #endif /* CONFIG_SYS_RAMBOOT */
183 * On MPC5200B we need to set the special configuration delay in the
184 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
185 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
187 * "The SDelay should be written to a value of 0x00000004. It is
188 * required to account for changes caused by normal wafer processing
193 if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
194 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
195 __asm__ volatile ("sync");
198 return dramsize + dramsize2;
201 int checkboard (void)
203 #if defined(CONFIG_PRS200)
204 puts ("Board: PRS200\n");
206 puts ("Board: MCC200\n");
211 int misc_init_r (void)
213 ulong flash_sup_end, snum;
216 * Adjust flash start and offset to detected values
218 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
219 gd->bd->bi_flashoffset = 0;
222 * Check if boot FLASH isn't max size
224 if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH_BASE)) {
226 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
227 START_REG(gd->bd->bi_flashstart);
228 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
229 STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);
232 * Re-check to get correct base address
234 flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
237 * Re-do flash protection upon new addresses
239 flash_protect (FLAG_PROTECT_CLEAR,
240 gd->bd->bi_flashstart, 0xffffffff,
241 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
243 /* Monitor protection ON by default */
244 flash_protect (FLAG_PROTECT_SET,
245 CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
246 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
248 /* Environment protection ON by default */
249 flash_protect (FLAG_PROTECT_SET,
251 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
252 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
254 /* Redundant environment protection ON by default */
255 flash_protect (FLAG_PROTECT_SET,
256 CONFIG_ENV_ADDR_REDUND,
257 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
258 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
261 if (gd->bd->bi_flashsize > (32 << 20)) {
262 /* Unprotect the upper bank of the Flash */
263 *(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6);
264 flash_protect (FLAG_PROTECT_CLEAR,
265 flash_info[0].start[0] + flash_info[0].size / 2,
266 (flash_info[0].start[0] - 1) + flash_info[0].size,
268 *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
269 printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n");
270 flash_info[0].size = 32 << 20;
271 for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20);
272 flash_info[0].start[snum] < flash_sup_end;
274 flash_info[0].sector_count = snum;
277 #ifdef CONFIG_AUTO_UPDATE
284 static struct pci_controller hose;
286 extern void pci_mpc5xxx_init(struct pci_controller *);
288 void pci_init_board(void)
290 pci_mpc5xxx_init(&hose);
294 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
296 void init_ide_reset (void)
298 debug ("init_ide_reset\n");
302 void ide_set_reset (int idereset)
304 debug ("ide_reset(%d)\n", idereset);
309 #if defined(CONFIG_CMD_DOC)
312 doc_probe (CONFIG_SYS_DOC_BASE);