2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 /* Two MT48LC8M32B2 for 32 MB */
32 /* #include "mt48lc8m32b2-6-7.h" */
34 /* One MT48LC16M32S2 for 64 MB */
35 #include "mt48lc16m32s2-75.h"
37 DECLARE_GLOBAL_DATA_PTR;
39 extern flash_info_t flash_info[]; /* FLASH chips info */
41 ulong flash_get_size (ulong base, int banknum);
44 static void sdram_start (int hi_addr)
46 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
48 /* unlock mode register */
49 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
50 __asm__ volatile ("sync");
52 /* precharge all banks */
53 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
54 __asm__ volatile ("sync");
57 /* set mode register: extended mode */
58 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
59 __asm__ volatile ("sync");
61 /* set mode register: reset DLL */
62 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
63 __asm__ volatile ("sync");
66 /* precharge all banks */
67 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
68 __asm__ volatile ("sync");
71 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
72 __asm__ volatile ("sync");
74 /* set mode register */
75 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
76 __asm__ volatile ("sync");
78 /* normal operation */
79 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
80 __asm__ volatile ("sync");
87 * ATTENTION: Although partially referenced initdram does NOT make real use
88 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
89 * is something else than 0x00000000.
92 long int initdram (int board_type)
99 /* setup SDRAM chip selects */
100 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
101 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
102 __asm__ volatile ("sync");
104 /* setup config registers */
105 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
106 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
107 __asm__ volatile ("sync");
111 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
112 __asm__ volatile ("sync");
115 /* find RAM size using SDRAM CS0 only */
117 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
119 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
127 /* memory smaller than 1MB is impossible */
128 if (dramsize < (1 << 20)) {
132 /* set SDRAM CS0 size according to the amount of RAM found */
134 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
136 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
139 /* let SDRAM CS1 start right after CS0 */
140 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
142 /* find RAM size using SDRAM CS1 only */
145 test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
148 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
157 /* memory smaller than 1MB is impossible */
158 if (dramsize2 < (1 << 20)) {
162 /* set SDRAM CS1 size according to the amount of RAM found */
164 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
165 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
167 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
170 #else /* CFG_RAMBOOT */
172 /* retrieve size of memory connected to SDRAM CS0 */
173 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
174 if (dramsize >= 0x13) {
175 dramsize = (1 << (dramsize - 0x13)) << 20;
180 /* retrieve size of memory connected to SDRAM CS1 */
181 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
182 if (dramsize2 >= 0x13) {
183 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
188 #endif /* CFG_RAMBOOT */
190 return dramsize + dramsize2;
193 int checkboard (void)
195 puts ("Board: MCC200\n");
199 int misc_init_r (void)
202 * Adjust flash start and offset to detected values
204 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
205 gd->bd->bi_flashoffset = 0;
208 * Check if boot FLASH isn't max size
210 if (gd->bd->bi_flashsize < (0 - CFG_FLASH_BASE)) {
212 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
213 START_REG(gd->bd->bi_flashstart);
214 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
215 STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);
218 * Re-check to get correct base address
220 flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
223 * Re-do flash protection upon new addresses
225 flash_protect (FLAG_PROTECT_CLEAR,
226 gd->bd->bi_flashstart, 0xffffffff,
227 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
229 /* Monitor protection ON by default */
230 flash_protect (FLAG_PROTECT_SET,
231 CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
232 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
234 /* Environment protection ON by default */
235 flash_protect (FLAG_PROTECT_SET,
237 CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
238 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
240 /* Redundant environment protection ON by default */
241 flash_protect (FLAG_PROTECT_SET,
243 CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
244 &flash_info[CFG_MAX_FLASH_BANKS - 1]);
247 if (gd->bd->bi_flashsize > (32 << 20)) {
248 /* Unprotect the upper bank of the Flash */
249 *(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6);
250 flash_protect (FLAG_PROTECT_CLEAR,
251 flash_info[0].start[0] + flash_info[0].size / 2,
252 (flash_info[0].start[0] + flash_info[0].size) / 2 - 1,
254 *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
261 static struct pci_controller hose;
263 extern void pci_mpc5xxx_init(struct pci_controller *);
265 void pci_init_board(void)
267 pci_mpc5xxx_init(&hose);
271 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
273 void init_ide_reset (void)
275 debug ("init_ide_reset\n");
279 void ide_set_reset (int idereset)
281 debug ("ide_reset(%d)\n", idereset);
284 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
286 #if (CONFIG_COMMANDS & CFG_CMD_DOC)
287 extern void doc_probe (ulong physadr);
290 doc_probe (CFG_DOC_BASE);