1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
13 #define EXT_DEVICE_CHANNEL_3 (0x30000000)
14 #define EXT_DEVICE_CHANNEL_2 (0x20000000)
15 #define EXT_DEVICE_CHANNEL_1 (0x10000000)
16 #define EXT_CPU_ACCESS_ACTIVE (0x00000001)
17 #define EXT_DMA_ACCESS_ACTIVE (1 << 14)
18 #define EXT_CPU_IORDY_SL (0x00000001)
20 #define EBI_CPU_WRITE (1 << 31)
21 #define EBI_CPU_ID_SHIFT (28)
22 #define EBI_CPU_ADDR_MASK ~(~0UL << EBI_CPU_ID_SHIFT)
24 /* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD1 */
25 #define ADDR_LATCH_ENABLE 0
26 #define ADDR_ACTIVATION 4
27 #define CHIP_SELECT_START 8
28 #define OUTPUT_ENABLE_START 12
30 #define READ_DURATION 20
32 /* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD2 */
33 #define OUTPUT_ENABLE_END 0
34 #define CHIP_SELECT_END 4
35 #define ADDR_DEACTIVATION 8
36 #define RECOVER_TIME 12
39 /* various bits in configuration register EBI_DEV[01]_CONFIG1 */
40 #define EBI_EXTERNAL_DATA_8 (1 << 8)
41 #define EBI_EXT_ADDR_SHIFT (1 << 22)
42 #define EBI_EXTERNAL_DATA_16 EBI_EXT_ADDR_SHIFT
43 #define EBI_CHIP_SELECT_1 0x2
44 #define EBI_CHIP_SELECT_2 0x4
45 #define EBI_BUSY_EN_RD (1 << 12)
46 #define DIR_ACCESS_WRITE (1 << 20)
47 #define DIR_ACCESS_MASK (1 << 20)
49 /* various bits in configuration register EBI_DEV[01]_CONFIG2 */
50 #define ADDRESS_INCREMENT_ON 0x0
51 #define ADDRESS_INCREMENT_OFF 0x100
52 #define QUEUE_LENGTH_1 0x40
53 #define QUEUE_LENGTH_2 0x80
54 #define QUEUE_LENGTH_3 0xC0
55 #define QUEUE_LENGTH_4 0
56 #define CPU_TRANSFER_SIZE_32 0
57 #define CPU_TRANSFER_SIZE_16 0x10
58 #define CPU_TRANSFER_SIZE_8 0x20
59 #define READ_ENDIANNESS_ABCD 0
60 #define READ_ENDIANNESS_DCBA 0x4
61 #define READ_ENDIANNESS_BADC 0x8
62 #define READ_ENDIANNESS_CDAB 0xC
63 #define WRITE_ENDIANNESS_ABCD 0
64 #define WRITE_ENDIANNESS_DCBA 0x1
65 #define WRITE_ENDIANNESS_BADC 0x2
66 #define WRITE_ENDIANNESS_CDAB 0x3
68 /* various bits in configuration register EBI_CTRL_SIG_ACTLV */
69 #define IORDY_ACTIVELEVEL_HIGH (1 << 14)
70 #define ALE_ACTIVELEVEL_HIGH (1 << 8)
72 /* bits in register EBI_SIG_LEVEL */
73 #define IORDY_LEVEL_MASK 1
75 static inline void ebi_wait(void)
77 while (reg_read(EBI_STATUS(EBI_BASE)) & EXT_CPU_ACCESS_ACTIVE)