2 * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
4 * Copyright (C) 2006 Micronas GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * Premium & Platinum register addresses/definitions seem to be
24 * identical, so we only need to use one file for both platforms.
27 #ifndef _REG_FWSRAM_H_
28 #define _REG_FWSRAM_H_
30 #define FWSRAM_BASE 0x00030000
32 /* Relative offsets of the register adresses */
34 #define FWSRAM_SR_ADDR_OFFSET_OFFS 0x00002000
35 #define FWSRAM_SR_ADDR_OFFSET(base) ((base) + FWSRAM_SR_ADDR_OFFSET_OFFS)
36 #define FWSRAM_TOP_BOOT_LOG_OFFS 0x00002004
37 #define FWSRAM_TOP_BOOT_LOG(base) ((base) + FWSRAM_TOP_BOOT_LOG_OFFS)
38 #define FWSRAM_TOP_ROM_KBIST_OFFS 0x00002008
39 #define FWSRAM_TOP_ROM_KBIST(base) ((base) + FWSRAM_TOP_ROM_KBIST_OFFS)
40 #define FWSRAM_TOP_CID1_H_OFFS 0x0000200C
41 #define FWSRAM_TOP_CID1_H(base) ((base) + FWSRAM_TOP_CID1_H_OFFS)
42 #define FWSRAM_TOP_CID1_L_OFFS 0x00002010
43 #define FWSRAM_TOP_CID1_L(base) ((base) + FWSRAM_TOP_CID1_L_OFFS)
44 #define FWSRAM_TOP_CID2_H_OFFS 0x00002014
45 #define FWSRAM_TOP_CID2_H(base) ((base) + FWSRAM_TOP_CID2_H_OFFS)
46 #define FWSRAM_TOP_CID2_L_OFFS 0x00002018
47 #define FWSRAM_TOP_CID2_L(base) ((base) + FWSRAM_TOP_CID2_L_OFFS)
48 #define FWSRAM_TOP_TDO_CFG_OFFS 0x0000203C
49 #define FWSRAM_TOP_TDO_CFG(base) ((base) + FWSRAM_TOP_TDO_CFG_OFFS)
50 #define FWSRAM_TOP_GPIO2_0_CFG_OFFS 0x00002040
51 #define FWSRAM_TOP_GPIO2_0_CFG(base) ((base) + FWSRAM_TOP_GPIO2_0_CFG_OFFS)
52 #define FWSRAM_TOP_GPIO2_1_CFG_OFFS 0x00002044
53 #define FWSRAM_TOP_GPIO2_1_CFG(base) ((base) + FWSRAM_TOP_GPIO2_1_CFG_OFFS)
54 #define FWSRAM_TOP_GPIO2_2_CFG_OFFS 0x00002048
55 #define FWSRAM_TOP_GPIO2_2_CFG(base) ((base) + FWSRAM_TOP_GPIO2_2_CFG_OFFS)
56 #define FWSRAM_TOP_GPIO2_3_CFG_OFFS 0x0000204C
57 #define FWSRAM_TOP_GPIO2_3_CFG(base) ((base) + FWSRAM_TOP_GPIO2_3_CFG_OFFS)
58 #define FWSRAM_TOP_GPIO2_4_CFG_OFFS 0x00002050
59 #define FWSRAM_TOP_GPIO2_4_CFG(base) ((base) + FWSRAM_TOP_GPIO2_4_CFG_OFFS)
60 #define FWSRAM_TOP_GPIO2_5_CFG_OFFS 0x00002054
61 #define FWSRAM_TOP_GPIO2_5_CFG(base) ((base) + FWSRAM_TOP_GPIO2_5_CFG_OFFS)
62 #define FWSRAM_TOP_GPIO2_6_CFG_OFFS 0x00002058
63 #define FWSRAM_TOP_GPIO2_6_CFG(base) ((base) + FWSRAM_TOP_GPIO2_6_CFG_OFFS)
64 #define FWSRAM_TOP_GPIO2_7_CFG_OFFS 0x0000205C
65 #define FWSRAM_TOP_GPIO2_7_CFG(base) ((base) + FWSRAM_TOP_GPIO2_7_CFG_OFFS)
66 #define FWSRAM_TOP_SCL_CFG_OFFS 0x00002060
67 #define FWSRAM_TOP_SCL_CFG(base) ((base) + FWSRAM_TOP_SCL_CFG_OFFS)
68 #define FWSRAM_TOP_SDA_CFG_OFFS 0x00002064
69 #define FWSRAM_TOP_SDA_CFG(base) ((base) + FWSRAM_TOP_SDA_CFG_OFFS)
70 #define FWSRAM_NO_MCM_FLASH_OFFS 0x00002068
71 #define FWSRAM_NO_MCM_FLASH(base) ((base) + FWSRAM_NO_MCM_FLASH_OFFS)