1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
5 * Copyright (C) 2006 Micronas GmbH
8 #ifndef _REG_EBI_PREMIUM_H_
9 #define _REG_EBI_PREMIUM_H_
11 #define EBI_BASE 0x00000000
13 /* Relative offsets of the register adresses */
15 #define EBI_CPU_IO_ACCS_OFFS 0x00000000
16 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS)
17 #define EBI_IO_ACCS_DATA_OFFS 0x00000004
18 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS)
19 #define EBI_CPU_IO_ACCS2_OFFS 0x00000008
20 #define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS)
21 #define EBI_IO_ACCS2_DATA_OFFS 0x0000000C
22 #define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS)
23 #define EBI_CTRL_OFFS 0x00000010
24 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS)
25 #define EBI_IRQ_MASK_OFFS 0x00000018
26 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS)
27 #define EBI_IRQ_MASK2_OFFS 0x0000001C
28 #define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS)
29 #define EBI_TAG1_SYS_ID_OFFS 0x00000030
30 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS)
31 #define EBI_TAG2_SYS_ID_OFFS 0x00000040
32 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS)
33 #define EBI_TAG3_SYS_ID_OFFS 0x00000050
34 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS)
35 #define EBI_TAG4_SYS_ID_OFFS 0x00000060
36 #define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS)
37 #define EBI_GEN_DMA_CTRL_OFFS 0x00000070
38 #define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS)
39 #define EBI_STATUS_OFFS 0x00000080
40 #define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS)
41 #define EBI_STATUS_DMA_CNT_OFFS 0x00000084
42 #define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS)
43 #define EBI_SIG_LEVEL_OFFS 0x00000088
44 #define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS)
45 #define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C
46 #define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS)
47 #define EBI_CRC_GEN_OFFS 0x00000090
48 #define EBI_CRC_GEN(base) ((base) + EBI_CRC_GEN_OFFS)
49 #define EBI_EXT_ADDR_OFFS 0x000000A0
50 #define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS)
51 #define EBI_IRQ_STATUS_OFFS 0x000000B0
52 #define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS)
53 #define EBI_IRQ_STATUS2_OFFS 0x000000B4
54 #define EBI_IRQ_STATUS2(base) ((base) + EBI_IRQ_STATUS2_OFFS)
55 #define EBI_EXT_MASTER_SRAM_HIGH_OFFS 0x000000C0
56 #define EBI_EXT_MASTER_SRAM_HIGH(base) ((base) + EBI_EXT_MASTER_SRAM_HIGH_OFFS)
57 #define EBI_EXT_MASTER_SRAM_LOW_OFFS 0x000000C4
58 #define EBI_EXT_MASTER_SRAM_LOW(base) ((base) + EBI_EXT_MASTER_SRAM_LOW_OFFS)
59 #define EBI_ECC0_OFFS 0x000000D0
60 #define EBI_ECC0(base) ((base) + EBI_ECC0_OFFS)
61 #define EBI_ECC1_OFFS 0x000000D4
62 #define EBI_ECC1(base) ((base) + EBI_ECC1_OFFS)
63 #define EBI_ECC2_OFFS 0x000000D8
64 #define EBI_ECC2(base) ((base) + EBI_ECC2_OFFS)
65 #define EBI_ECC3_OFFS 0x000000DC
66 #define EBI_ECC3(base) ((base) + EBI_ECC3_OFFS)
67 #define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100
68 #define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS)
69 #define EBI_DEV1_EXT_ACC_OFFS 0x00000104
70 #define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS)
71 #define EBI_DEV1_CONFIG1_OFFS 0x00000108
72 #define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS)
73 #define EBI_DEV1_CONFIG2_OFFS 0x0000010C
74 #define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS)
75 #define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110
76 #define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS)
77 #define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114
78 #define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS)
79 #define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118
80 #define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS)
81 #define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C
82 #define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS)
83 #define EBI_DEV1_DMA_ECC_CTRL_OFFS 0x00000120
84 #define EBI_DEV1_DMA_ECC_CTRL(base) ((base) + EBI_DEV1_DMA_ECC_CTRL_OFFS)
85 #define EBI_DEV1_TIM1_RD1_OFFS 0x00000124
86 #define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS)
87 #define EBI_DEV1_TIM1_RD2_OFFS 0x00000128
88 #define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS)
89 #define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C
90 #define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS)
91 #define EBI_DEV1_TIM1_WR2_OFFS 0x00000130
92 #define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS)
93 #define EBI_DEV1_TIM_EXT_OFFS 0x00000134
94 #define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS)
95 #define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138
96 #define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS)
97 #define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C
98 #define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS)
99 #define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140
100 #define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS)
101 #define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144
102 #define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS)
103 #define EBI_DEV1_TIM4_UDMA1_OFFS 0x00000148
104 #define EBI_DEV1_TIM4_UDMA1(base) ((base) + EBI_DEV1_TIM4_UDMA1_OFFS)
105 #define EBI_DEV1_TIM4_UDMA2_OFFS 0x0000014C
106 #define EBI_DEV1_TIM4_UDMA2(base) ((base) + EBI_DEV1_TIM4_UDMA2_OFFS)
107 #define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150
108 #define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS)
109 #define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200
110 #define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS)
111 #define EBI_DEV2_EXT_ACC_OFFS 0x00000204
112 #define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS)
113 #define EBI_DEV2_CONFIG1_OFFS 0x00000208
114 #define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS)
115 #define EBI_DEV2_CONFIG2_OFFS 0x0000020C
116 #define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS)
117 #define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210
118 #define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS)
119 #define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214
120 #define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS)
121 #define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218
122 #define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS)
123 #define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C
124 #define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS)
125 #define EBI_DEV2_DMA_ECC_CTRL_OFFS 0x00000220
126 #define EBI_DEV2_DMA_ECC_CTRL(base) ((base) + EBI_DEV2_DMA_ECC_CTRL_OFFS)
127 #define EBI_DEV2_TIM1_RD1_OFFS 0x00000224
128 #define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS)
129 #define EBI_DEV2_TIM1_RD2_OFFS 0x00000228
130 #define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS)
131 #define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C
132 #define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS)
133 #define EBI_DEV2_TIM1_WR2_OFFS 0x00000230
134 #define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS)
135 #define EBI_DEV2_TIM_EXT_OFFS 0x00000234
136 #define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS)
137 #define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238
138 #define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS)
139 #define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C
140 #define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS)
141 #define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240
142 #define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS)
143 #define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244
144 #define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS)
145 #define EBI_DEV2_TIM4_UDMA1_OFFS 0x00000248
146 #define EBI_DEV2_TIM4_UDMA1(base) ((base) + EBI_DEV2_TIM4_UDMA1_OFFS)
147 #define EBI_DEV2_TIM4_UDMA2_OFFS 0x0000024C
148 #define EBI_DEV2_TIM4_UDMA2(base) ((base) + EBI_DEV2_TIM4_UDMA2_OFFS)
149 #define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250
150 #define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS)
151 #define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300
152 #define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS)
153 #define EBI_DEV3_EXT_ACC_OFFS 0x00000304
154 #define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS)
155 #define EBI_DEV3_CONFIG1_OFFS 0x00000308
156 #define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS)
157 #define EBI_DEV3_CONFIG2_OFFS 0x0000030C
158 #define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS)
159 #define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310
160 #define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS)
161 #define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314
162 #define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS)
163 #define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318
164 #define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS)
165 #define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C
166 #define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS)
167 #define EBI_DEV3_DMA_ECC_CTRL_OFFS 0x00000320
168 #define EBI_DEV3_DMA_ECC_CTRL(base) ((base) + EBI_DEV3_DMA_ECC_CTRL_OFFS)
169 #define EBI_DEV3_TIM1_RD1_OFFS 0x00000324
170 #define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS)
171 #define EBI_DEV3_TIM1_RD2_OFFS 0x00000328
172 #define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS)
173 #define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C
174 #define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS)
175 #define EBI_DEV3_TIM1_WR2_OFFS 0x00000330
176 #define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS)
177 #define EBI_DEV3_TIM_EXT_OFFS 0x00000334
178 #define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS)
179 #define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338
180 #define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS)
181 #define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C
182 #define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS)
183 #define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340
184 #define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS)
185 #define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344
186 #define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS)
187 #define EBI_DEV3_TIM4_UDMA1_OFFS 0x00000348
188 #define EBI_DEV3_TIM4_UDMA1(base) ((base) + EBI_DEV3_TIM4_UDMA1_OFFS)
189 #define EBI_DEV3_TIM4_UDMA2_OFFS 0x0000034C
190 #define EBI_DEV3_TIM4_UDMA2(base) ((base) + EBI_DEV3_TIM4_UDMA2_OFFS)
191 #define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350
192 #define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS)
193 #define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400
194 #define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS)
195 #define EBI_DEV4_EXT_ACC_OFFS 0x00000404
196 #define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS)
197 #define EBI_DEV4_CONFIG1_OFFS 0x00000408
198 #define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS)
199 #define EBI_DEV4_CONFIG2_OFFS 0x0000040C
200 #define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS)
201 #define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410
202 #define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS)
203 #define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414
204 #define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS)
205 #define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418
206 #define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS)
207 #define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C
208 #define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS)
209 #define EBI_DEV4_DMA_ECC_CTRL_OFFS 0x00000420
210 #define EBI_DEV4_DMA_ECC_CTRL(base) ((base) + EBI_DEV4_DMA_ECC_CTRL_OFFS)
211 #define EBI_DEV4_TIM1_RD1_OFFS 0x00000424
212 #define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS)
213 #define EBI_DEV4_TIM1_RD2_OFFS 0x00000428
214 #define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS)
215 #define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C
216 #define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS)
217 #define EBI_DEV4_TIM1_WR2_OFFS 0x00000430
218 #define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS)
219 #define EBI_DEV4_TIM_EXT_OFFS 0x00000434
220 #define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS)
221 #define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438
222 #define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS)
223 #define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C
224 #define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS)
225 #define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440
226 #define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS)
227 #define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444
228 #define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS)
229 #define EBI_DEV4_TIM4_UDMA1_OFFS 0x00000448
230 #define EBI_DEV4_TIM4_UDMA1(base) ((base) + EBI_DEV4_TIM4_UDMA1_OFFS)
231 #define EBI_DEV4_TIM4_UDMA2_OFFS 0x0000044C
232 #define EBI_DEV4_TIM4_UDMA2(base) ((base) + EBI_DEV4_TIM4_UDMA2_OFFS)
233 #define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450
234 #define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS)
235 #define EBI_INTERLEAVE_CNT_OFFS 0x00000900
236 #define EBI_INTERLEAVE_CNT(base) ((base) + EBI_INTERLEAVE_CNT_OFFS)
237 #define EBI_CNT_FL_PROGR_OFFS 0x00000904
238 #define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS)
239 #define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C
240 #define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS)
241 #define EBI_CNT_WAIT_RDY_OFFS 0x00000914
242 #define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS)
243 #define EBI_CNT_ACK_OFFS 0x00000918
244 #define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS)
245 #define EBI_GENIO1_CONFIG1_OFFS 0x00000A00
246 #define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS)
247 #define EBI_GENIO1_CONFIG2_OFFS 0x00000A04
248 #define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS)
249 #define EBI_GENIO1_CONFIG3_OFFS 0x00000A08
250 #define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS)
251 #define EBI_GENIO2_CONFIG1_OFFS 0x00000A10
252 #define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS)
253 #define EBI_GENIO2_CONFIG2_OFFS 0x00000A14
254 #define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS)
255 #define EBI_GENIO2_CONFIG3_OFFS 0x00000A18
256 #define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS)
257 #define EBI_GENIO3_CONFIG1_OFFS 0x00000A20
258 #define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS)
259 #define EBI_GENIO3_CONFIG2_OFFS 0x00000A24
260 #define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS)
261 #define EBI_GENIO3_CONFIG3_OFFS 0x00000A28
262 #define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS)
263 #define EBI_GENIO4_CONFIG1_OFFS 0x00000A30
264 #define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS)
265 #define EBI_GENIO4_CONFIG2_OFFS 0x00000A34
266 #define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS)
267 #define EBI_GENIO4_CONFIG3_OFFS 0x00000A38
268 #define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS)
269 #define EBI_GENIO5_CONFIG1_OFFS 0x00000A40
270 #define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS)
271 #define EBI_GENIO5_CONFIG2_OFFS 0x00000A44
272 #define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS)
273 #define EBI_GENIO5_CONFIG3_OFFS 0x00000A48
274 #define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS)
projects / u-boot / blob