4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * James Dougherty (jfd@cs.stanford.edu)
9 * SPDX-License-Identifier: GPL-2.0+
13 * PCI Configuration space access support for MPC824x/MPC107 PCI Bridge
22 * Promise ATA/66 support.
24 #define XFER_PIO_4 0x0C /* 0000|1100 */
25 #define XFER_PIO_3 0x0B /* 0000|1011 */
26 #define XFER_PIO_2 0x0A /* 0000|1010 */
27 #define XFER_PIO_1 0x09 /* 0000|1001 */
28 #define XFER_PIO_0 0x08 /* 0000|1000 */
29 #define XFER_PIO_SLOW 0x00 /* 0000|0000 */
38 pdc202xx_decode_registers (unsigned char registers, unsigned char value)
40 unsigned char bit = 0, bit1 = 0, bit2 = 0;
44 printf(" A Register ");
45 if (value & 0x80) printf("SYNC_IN ");
46 if (value & 0x40) printf("ERRDY_EN ");
47 if (value & 0x20) printf("IORDY_EN ");
48 if (value & 0x10) printf("PREFETCH_EN ");
49 if (value & 0x08) { printf("PA3 ");bit2 |= 0x08; }
50 if (value & 0x04) { printf("PA2 ");bit2 |= 0x04; }
51 if (value & 0x02) { printf("PA1 ");bit2 |= 0x02; }
52 if (value & 0x01) { printf("PA0 ");bit2 |= 0x01; }
53 printf("PIO(A) = %d ", bit2);
57 printf(" B Register ");
58 if (value & 0x80) { printf("MB2 ");bit1 |= 0x80; }
59 if (value & 0x40) { printf("MB1 ");bit1 |= 0x40; }
60 if (value & 0x20) { printf("MB0 ");bit1 |= 0x20; }
61 printf("DMA(B) = %d ", bit1 >> 5);
62 if (value & 0x10) printf("PIO_FORCED/PB4 ");
63 if (value & 0x08) { printf("PB3 ");bit2 |= 0x08; }
64 if (value & 0x04) { printf("PB2 ");bit2 |= 0x04; }
65 if (value & 0x02) { printf("PB1 ");bit2 |= 0x02; }
66 if (value & 0x01) { printf("PB0 ");bit2 |= 0x01; }
67 printf("PIO(B) = %d ", bit2);
71 printf(" C Register ");
72 if (value & 0x80) printf("DMARQp ");
73 if (value & 0x40) printf("IORDYp ");
74 if (value & 0x20) printf("DMAR_EN ");
75 if (value & 0x10) printf("DMAW_EN ");
77 if (value & 0x08) { printf("MC3 ");bit2 |= 0x08; }
78 if (value & 0x04) { printf("MC2 ");bit2 |= 0x04; }
79 if (value & 0x02) { printf("MC1 ");bit2 |= 0x02; }
80 if (value & 0x01) { printf("MC0 ");bit2 |= 0x01; }
81 printf("DMA(C) = %d ", bit2);
84 printf(" D Register ");
89 printf("\n %s ", (registers & REG_D) ? "DP" :
90 (registers & REG_C) ? "CP" :
91 (registers & REG_B) ? "BP" :
92 (registers & REG_A) ? "AP" : "ERROR");
93 for (bit=128;bit>0;bit/=2)
94 printf("%s", (value & bit) ? "1" : "0");
99 * Promise ATA/66 Support: configure Promise ATA66 card in specified mode.
102 pdc202xx_tune_chipset (pci_dev_t dev, int drive, unsigned char speed)
104 unsigned short drive_conf;
106 unsigned char drive_pci, AP, BP, CP, DP;
107 unsigned char TA = 0, TB = 0;
110 case 0: drive_pci = 0x60; break;
111 case 1: drive_pci = 0x64; break;
112 case 2: drive_pci = 0x68; break;
113 case 3: drive_pci = 0x6c; break;
117 pci_read_config_word(dev, drive_pci, &drive_conf);
118 pci_read_config_byte(dev, (drive_pci), &AP);
119 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
120 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
121 pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
123 if ((AP & 0x0F) || (BP & 0x07)) {
124 /* clear PIO modes of lower 8421 bits of A Register */
125 pci_write_config_byte(dev, (drive_pci), AP & ~0x0F);
126 pci_read_config_byte(dev, (drive_pci), &AP);
128 /* clear PIO modes of lower 421 bits of B Register */
129 pci_write_config_byte(dev, (drive_pci)|0x01, BP & ~0x07);
130 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
132 pci_read_config_byte(dev, (drive_pci), &AP);
133 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
136 pci_read_config_byte(dev, (drive_pci), &AP);
137 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
138 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
141 case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
142 case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
143 case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
144 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
146 default: TA = 0x09; TB = 0x13; break;
149 pci_write_config_byte(dev, (drive_pci), AP|TA);
150 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
152 pci_read_config_byte(dev, (drive_pci), &AP);
153 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
154 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
155 pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
158 #ifdef PDC202XX_DEBUG
159 pdc202xx_decode_registers(REG_A, AP);
160 pdc202xx_decode_registers(REG_B, BP);
161 pdc202xx_decode_registers(REG_C, CP);
162 pdc202xx_decode_registers(REG_D, DP);
167 * Show/Init PCI devices on the specified bus number.
170 void pci_mousse_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
174 switch(PCI_DEV(dev)) {
185 pci_write_config_dword(dev, PCI_INTERRUPT_LINE, line);
188 void pci_mousse_setup_pdc202xx(struct pci_controller *hose, pci_dev_t dev,
189 struct pci_config_table *_)
191 unsigned short vendorId;
192 unsigned int mbar0, cmd;
195 pci_read_config_word(dev, PCI_VENDOR_ID, &vendorId);
197 if(vendorId == PCI_VENDOR_ID_PROMISE || vendorId == PCI_VENDOR_ID_CMD){
198 /* PDC 202xx card is handled differently, it is a bootable
199 * device and needs all 5 MBAR's configured
201 for(bar = 0; bar < 5; bar++){
202 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0);
203 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, ~0);
204 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0);
206 printf(" ATA_bar[%d] = %dbytes\n", bar,
207 ~(mbar0 & PCI_BASE_ADDRESS_MEM_MASK) + 1);
211 /* Program all BAR's */
212 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PROMISE_MBAR0);
213 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, PROMISE_MBAR1);
214 pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, PROMISE_MBAR2);
215 pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, PROMISE_MBAR3);
216 pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, PROMISE_MBAR4);
217 pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, PROMISE_MBAR5);
219 for(bar = 0; bar < 5; bar++){
220 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0);
222 printf(" ATA_bar[%d]@0x%x\n", bar, mbar0);
226 /* Enable ROM Expansion base */
227 pci_write_config_dword(dev, PCI_ROM_ADDRESS, PROMISE_MBAR5|1);
229 /* Io enable, Memory enable, master enable */
230 pci_read_config_dword(dev, PCI_COMMAND, &cmd);
232 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
233 pci_write_config_dword(dev, PCI_COMMAND, cmd);
235 /* Breath some life into the controller */
236 for( a = 0; a < 4; a++)
237 pdc202xx_tune_chipset(dev, a, XFER_PIO_0);
241 static struct pci_config_table pci_sandpoint_config_table[] = {
242 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 0x0e, 0x00,
243 pci_mousse_setup_pdc202xx },
244 #ifndef CONFIG_PCI_PNP
245 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 0x0d, 0x00,
246 pci_cfgfunc_config_device, {PCI_ENET_IOADDR,
249 PCI_COMMAND_MASTER}},
250 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
251 pci_cfgfunc_config_device, {PCI_SLOT_IOADDR,
254 PCI_COMMAND_MASTER}},
259 struct pci_controller hose = {
260 config_table: pci_sandpoint_config_table,
261 fixup_irq: pci_mousse_fixup_irq,
264 void pci_init_board(void)
266 pci_mpc824x_init(&hose);