2 * (C) Copyright 2001-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Modified during 2001 by
6 * Advanced Communications Technologies (Australia) Pty. Ltd.
7 * Howard Walker, Tuong Vu-Dinh
9 * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
10 * Added support for the 16M dram simm on the 8260ads boards
12 * (C) Copyright 2003-2004 Arabella Software Ltd.
13 * Yuli Barcohen <yuli@arabellasw.com>
14 * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
16 * Copyright (c) 2005 MontaVista Software, Inc.
17 * Vitaly Bordug <vbordug@ru.mvista.com>
18 * Added support for PCI.
20 * See file CREDITS for list of people who contributed to this
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License as
25 * published by the Free Software Foundation; either version 2 of
26 * the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
42 #include <asm/m8260_pci.h>
51 * I/O Port configuration table
53 * if conf is 1, then that port pin will be configured at boot time
54 * according to the five values podr/pdir/ppar/psor/pdat for that entry
57 #define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
58 #define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
59 #define CFG_FCC3 (CONFIG_ETHER_INDEX == 3)
61 const iop_conf_t iop_conf_tab[4][32] = {
63 /* Port A configuration */
64 { /* conf ppar psor pdir podr pdat */
65 /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
66 /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
67 /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
68 /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
69 /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
70 /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
71 /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
72 /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
73 /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
74 /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
75 /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
76 /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
77 /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
78 /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
79 /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
80 /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
81 /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
82 /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
83 /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
84 /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
85 /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
86 /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
87 /* PA9 */ { 0, 0, 0, 0, 0, 0 }, /* PA9 */
88 /* PA8 */ { 0, 0, 0, 0, 0, 0 }, /* PA8 */
89 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
90 /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
91 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
92 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
93 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
94 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
95 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
96 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
99 /* Port B configuration */
100 { /* conf ppar psor pdir podr pdat */
101 /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
102 /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
103 /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
104 /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
105 /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
106 /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
107 /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
108 /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
109 /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
110 /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
111 /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
112 /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
113 /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
114 /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
115 /* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
116 /* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
117 /* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
118 /* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
119 /* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */
120 /* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
121 /* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
122 /* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
123 /* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
124 /* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
125 /* PB7 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
126 /* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
127 /* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
128 /* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
129 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
130 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
131 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
132 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
136 { /* conf ppar psor pdir podr pdat */
137 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
138 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
139 /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
140 /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
141 /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
142 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
143 /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
144 /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
145 /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
146 /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */
147 /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */
148 /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
149 #if CONFIG_ADSTYPE == CFG_8272ADS
150 /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
151 /* PC18 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
152 /* PC17 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */
153 /* PC16 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */
155 /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
156 /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
157 /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
158 /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
159 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
160 /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
161 /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
162 /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
163 /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
164 /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
165 #if CONFIG_ADSTYPE == CFG_8272ADS
166 /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
167 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
169 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
170 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
171 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
172 /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
173 /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
174 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
175 /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
176 /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
177 /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
178 /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
179 /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
180 /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
184 { /* conf ppar psor pdir podr pdat */
185 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */
186 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */
187 /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
188 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
189 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
190 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
191 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
192 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
193 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
194 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
195 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
196 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
197 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
198 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
199 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
200 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
201 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
202 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
203 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
204 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
205 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
206 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
207 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
208 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
209 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
210 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
211 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
212 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
213 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
214 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
215 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
216 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
220 void reset_phy (void)
222 vu_long *bcsr = (vu_long *)CFG_BCSR;
225 #if CFG_PHY_ADDR == 0
226 bcsr[1] &= ~(FETHIEN1 | FETH1_RST);
228 bcsr[1] |= FETH1_RST;
230 bcsr[3] &= ~(FETHIEN2 | FETH2_RST);
232 bcsr[3] |= FETH2_RST;
233 #endif /* CFG_PHY_ADDR == 0 */
236 #if CONFIG_ADSTYPE >= CFG_PQ2FADS
238 * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
239 * Enable autonegotiation.
241 miiphy_write(CFG_PHY_ADDR, 16, 0x610);
242 miiphy_write(CFG_PHY_ADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
245 * Ethernet PHY is configured (by means of configuration pins)
246 * to work at 10Mb/s only. We reconfigure it using MII
247 * to advertise all capabilities, including 100Mb/s, and
248 * restart autonegotiation.
250 miiphy_write(CFG_PHY_ADDR, PHY_ANAR, 0x01E1); /* Advertise all capabilities */
251 miiphy_write(CFG_PHY_ADDR, PHY_DCR, 0x0000); /* Do not bypass Rx/Tx (de)scrambler */
252 miiphy_write(CFG_PHY_ADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
253 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
254 #endif /* CONFIG_MII */
258 typedef struct pci_ic_s {
259 unsigned long pci_int_stat;
260 unsigned long pci_int_mask;
264 int board_early_init_f (void)
266 vu_long *bcsr = (vu_long *)CFG_BCSR;
269 volatile pci_ic_t* pci_ic = (pci_ic_t *) CFG_PCI_INT;
271 /* mask alll the PCI interrupts */
272 pci_ic->pci_int_mask |= 0xfff00000;
274 #if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1)
275 bcsr[1] &= ~RS232EN_1;
277 #if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1)
278 bcsr[1] &= ~RS232EN_2;
281 #if CONFIG_ADSTYPE != CFG_8260ADS /* PCI mode can be selected */
282 #if CONFIG_ADSTYPE == CFG_PQ2FADS
283 if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */
284 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
286 volatile immap_t *immap = (immap_t *) CFG_IMMR;
288 immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
289 immap->im_siu_conf.sc_siumcr =
290 (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
293 #endif /* CONFIG_ADSTYPE != CFG_8260ADS */
298 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
300 long int initdram (int board_type)
302 #if CONFIG_ADSTYPE == CFG_PQ2FADS
304 #elif CONFIG_ADSTYPE == CFG_8272ADS
311 volatile immap_t *immap = (immap_t *) CFG_IMMR;
312 volatile memctl8260_t *memctl = &immap->im_memctl;
313 volatile uchar *ramaddr, c = 0xff;
320 immap->im_siu_conf.sc_ppc_acr = 0x00000002;
321 immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
322 immap->im_siu_conf.sc_tescr1 = 0x00004000;
324 memctl->memc_mptpr = CFG_MPTPR;
325 #ifdef CFG_LSDRAM_BASE
327 Initialise local bus SDRAM only if the pins
328 are configured as local bus pins and not as PCI.
329 The configuration is determined by the HRCW.
331 if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
332 memctl->memc_lsrt = CFG_LSRT;
333 #if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */
334 memctl->memc_or3 = 0xFF803280;
335 memctl->memc_br3 = CFG_LSDRAM_BASE | 0x00001861;
337 memctl->memc_or4 = 0xFFC01480;
338 memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861;
339 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
340 memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
341 ramaddr = (uchar *) CFG_LSDRAM_BASE;
343 memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
344 for (i = 0; i < 8; i++)
346 memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
348 memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
350 #endif /* CFG_LSDRAM_BASE */
352 /* Init 60x bus SDRAM */
353 #ifdef CONFIG_SPD_EEPROM
356 uint pbi, bsel, rowst, lsb, tmp;
358 i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));
360 /* Bank-based interleaving is not supported for physical bank
361 sizes greater than 128MB which is encoded as 0x20 in SPD
363 pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
364 msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */
365 or = ~(msize - 1) << 20; /* SDAM */
366 switch (spd.nbanks) { /* BPD */
379 lsb = 3; /* For 64-bit port, lsb is 3 bits */
381 if (pbi) { /* Bus partition depends on interleaving */
382 rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
383 or |= (rowst << 9); /* ROWST */
385 rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
386 or |= ((rowst * 2 - 12) << 9); /* ROWST */
388 or |= ((spd.nrow_addr - 9) << 6); /* NUMR */
390 psdmr = (pbi << 31); /* PBI */
391 /* Bus multiplexing parameters */
392 tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */
393 psdmr |= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */
394 psdmr |= ((tmp - 3 - 12) << 21); /* BSMA */
396 tmp = (31 - lsb - 10) - tmp;
397 /* Pin connected to SDA10 is (31 - lsb - 10).
398 rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
399 so (rowst + tmp) alternates with AP.
401 if (pbi) /* Table 10-7 */
402 psdmr |= ((10 - (rowst + tmp)) << 18); /* SDA10 */
404 psdmr |= ((12 - (rowst + tmp)) << 18); /* SDA10 */
406 /* SDRAM device-specific parameters */
407 tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */
408 switch (tmp) { /* RFRC */
419 psdmr |= ((tmp - 2) << 15);
424 psdmr |= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */
425 psdmr |= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */
426 /* BL=0 because for 64-bit SDRAM burst length must be 4 */
428 for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
430 switch (i) { /* WRC */
440 /* EAMUX=0 - no external address multiplexing */
441 /* BUFCMD=0 - no external buffers */
442 for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
446 switch (spd.refresh & 0x7F) {
465 psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
466 ((memctl->memc_mptpr >> 8) + 1)) - 1;
468 printf ("\nDIMM type: %-18.18s\n", spd.mpart);
469 printf ("SPD size: %d\n", spd.info_size);
470 printf ("EEPROM size: %d\n", 1 << spd.chip_size);
471 printf ("Memory type: %d\n", spd.mem_type);
472 printf ("Row addr: %d\n", spd.nrow_addr);
473 printf ("Column addr: %d\n", spd.ncol_addr);
474 printf ("# of rows: %d\n", spd.nrows);
475 printf ("Row density: %d\n", spd.row_dens);
476 printf ("# of banks: %d\n", spd.nbanks);
477 printf ("Data width: %d\n",
478 256 * spd.dataw_msb + spd.dataw_lsb);
479 printf ("Chip width: %d\n", spd.primw);
480 printf ("Refresh rate: %02X\n", spd.refresh);
481 printf ("CAS latencies: %02X\n", spd.cas_lat);
482 printf ("Write latencies: %02X\n", spd.write_lat);
483 printf ("tRP: %d\n", spd.trp);
484 printf ("tRCD: %d\n", spd.trcd);
486 printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
487 #endif /* SPD_DEBUG */
489 #else /* !CONFIG_SPD_EEPROM */
493 #endif /* CONFIG_SPD_EEPROM */
494 memctl->memc_psrt = psrt;
495 memctl->memc_or2 = or;
496 memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;
497 ramaddr = (uchar *) CFG_SDRAM_BASE;
498 memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */
500 memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */
501 for (i = 0; i < 8; i++)
504 memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */
506 memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */
508 #endif /* CFG_RAMBOOT */
510 /* return total 60x bus SDRAM size */
511 return (msize * 1024 * 1024);
514 int checkboard (void)
516 #if CONFIG_ADSTYPE == CFG_8260ADS
517 puts ("Board: Motorola MPC8260ADS\n");
518 #elif CONFIG_ADSTYPE == CFG_8266ADS
519 puts ("Board: Motorola MPC8266ADS\n");
520 #elif CONFIG_ADSTYPE == CFG_PQ2FADS
521 puts ("Board: Motorola PQ2FADS-ZU\n");
522 #elif CONFIG_ADSTYPE == CFG_8272ADS
523 puts ("Board: Motorola MPC8272ADS\n");
525 puts ("Board: unknown\n");
531 struct pci_controller hose;
533 extern void pci_mpc8250_init(struct pci_controller *);
535 void pci_init_board(void)
537 pci_mpc8250_init(&hose);