2 * (C) Copyright 2001-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Modified during 2001 by
6 * Advanced Communications Technologies (Australia) Pty. Ltd.
7 * Howard Walker, Tuong Vu-Dinh
9 * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
10 * Added support for the 16M dram simm on the 8260ads boards
12 * (C) Copyright 2003 Arabella Software Ltd.
13 * Yuli Barcohen <yuli@arabellasw.com>
14 * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
16 * See file CREDITS for list of people who contributed to this
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
42 * I/O Port configuration table
44 * if conf is 1, then that port pin will be configured at boot time
45 * according to the five values podr/pdir/ppar/psor/pdat for that entry
48 const iop_conf_t iop_conf_tab[4][32] = {
50 /* Port A configuration */
51 { /* conf ppar psor pdir podr pdat */
52 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
53 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
54 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
55 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
56 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
57 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
58 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
59 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
60 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
61 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
62 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
63 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
64 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
65 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
66 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
67 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
68 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
69 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
70 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
71 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
72 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
73 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
74 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
75 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
76 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
77 /* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
78 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
79 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
80 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
81 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
82 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
83 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
86 /* Port B configuration */
87 { /* conf ppar psor pdir podr pdat */
88 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
89 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
90 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
91 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
92 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
93 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
94 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
95 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
96 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
97 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
98 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
99 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
100 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
101 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
102 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
103 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
104 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
105 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
106 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
107 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
108 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
109 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
110 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
111 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
112 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
113 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
114 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
115 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
116 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
117 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
118 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
119 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
123 { /* conf ppar psor pdir podr pdat */
124 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
125 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
126 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
127 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
128 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
129 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
130 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
131 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
132 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
133 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
134 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
135 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
136 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
137 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
138 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
139 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
140 /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
141 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
142 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
143 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
144 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
145 /* PC10 */ { 1, 1, 0, 0, 0, 0 }, /* LXT970 FETHMDC */
146 /* PC9 */ { 1, 1, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */
147 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
148 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
149 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
150 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
151 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
152 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
153 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
154 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
155 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
159 { /* conf ppar psor pdir podr pdat */
160 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
161 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
162 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
163 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
164 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
165 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
166 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
167 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
168 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
169 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
170 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
171 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
172 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
173 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
174 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
175 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
176 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
177 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
178 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
179 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
180 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
181 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
182 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
183 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
184 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
185 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
186 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
187 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
188 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
189 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
190 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
191 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
195 typedef struct bscr_ {
206 void reset_phy (void)
208 volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
210 /* reset the FEC port */
211 bcsr->bcsr1 &= ~FETH_RST;
212 bcsr->bcsr1 |= FETH_RST;
216 int board_pre_init (void)
218 volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
220 bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1;
225 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
227 long int initdram (int board_type)
229 volatile immap_t *immap = (immap_t *) CFG_IMMR;
230 volatile memctl8260_t *memctl = &immap->im_memctl;
231 volatile uchar *ramaddr, c = 0xff;
233 /* Initialisation is for 16MB DIMM the board is shipped with */
235 uint or = 0xFF000CA0;
236 uint psdmr = CFG_PSDMR;
237 uint psrt = CFG_PSRT;
242 immap->im_siu_conf.sc_ppc_acr = 0x00000002;
243 immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
244 immap->im_siu_conf.sc_tescr1 = 0x00004000;
246 memctl->memc_mptpr = CFG_MPTPR;
247 /* init local sdram, bank 4 */
248 memctl->memc_lsrt = 0x00000010;
249 memctl->memc_or4 = 0xFFC01480;
250 memctl->memc_br4 = 0x04001861;
251 memctl->memc_lsdmr = 0x2886A522;
252 ramaddr = (uchar *) CFG_LSDRAM_BASE;
254 memctl->memc_lsdmr = 0x0886A522;
255 for (i = 0; i < 8; i++) {
258 memctl->memc_lsdmr = 0x1886A522;
260 memctl->memc_lsdmr = 0x4086A522;
262 /* init sdram dimm */
263 #ifdef CONFIG_SPD_EEPROM
266 uint pbi, bsel, rowst, lsb, tmp;
268 i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));
270 /* Bank-based interleaving is not supported for physical bank
271 sizes greater than 128MB which is encoded as 0x20 in SPD
273 pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
274 msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */
275 or = ~(msize - 1) << 20; /* SDAM */
276 switch (spd.nbanks) { /* BPD */
289 lsb = 3; /* For 64-bit port, lsb is 3 bits */
291 if (pbi) { /* Bus partition depends on interleaving */
292 rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
293 or |= (rowst << 9); /* ROWST */
295 rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
296 or |= ((rowst * 2 - 12) << 9); /* ROWST */
298 or |= ((spd.nrow_addr - 9) << 6); /* NUMR */
300 psdmr = (pbi << 31); /* PBI */
301 /* Bus multiplexing parameters */
302 tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */
303 psdmr |= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */
304 psdmr |= ((tmp - 3 - 12) << 21); /* BSMA */
306 tmp = (31 - lsb - 10) - tmp;
307 /* Pin connected to SDA10 is (31 - lsb - 10).
308 rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
309 so (rowst + tmp) alternates with AP.
311 if (pbi) /* Table 10-7 */
312 psdmr |= ((10 - (rowst + tmp)) << 18); /* SDA10 */
314 psdmr |= ((12 - (rowst + tmp)) << 18); /* SDA10 */
316 /* SDRAM device-specific parameters */
317 tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */
318 switch (tmp) { /* RFRC */
329 psdmr |= ((tmp - 2) << 15);
334 psdmr |= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */
335 psdmr |= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */
336 /* BL=0 because for 64-bit SDRAM burst length must be 4 */
338 for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
340 switch (i) { /* WRC */
350 /* EAMUX=0 - no external address multiplexing */
351 /* BUFCMD=0 - no external buffers */
352 for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
356 switch (spd.refresh & 0x7F) {
375 psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
376 ((memctl->memc_mptpr >> 8) + 1)) - 1;
378 printf ("\nDIMM type: %-18.18s\n", spd.mpart);
379 printf ("SPD size: %d\n", spd.info_size);
380 printf ("EEPROM size: %d\n", 1 << spd.chip_size);
381 printf ("Memory type: %d\n", spd.mem_type);
382 printf ("Row addr: %d\n", spd.nrow_addr);
383 printf ("Column addr: %d\n", spd.ncol_addr);
384 printf ("# of rows: %d\n", spd.nrows);
385 printf ("Row density: %d\n", spd.row_dens);
386 printf ("# of banks: %d\n", spd.nbanks);
387 printf ("Data width: %d\n",
388 256 * spd.dataw_msb + spd.dataw_lsb);
389 printf ("Chip width: %d\n", spd.primw);
390 printf ("Refresh rate: %02X\n", spd.refresh);
391 printf ("CAS latencies: %02X\n", spd.cas_lat);
392 printf ("Write latencies: %02X\n", spd.write_lat);
393 printf ("tRP: %d\n", spd.trp);
394 printf ("tRCD: %d\n", spd.trcd);
396 printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
397 #endif /* SPD_DEBUG */
399 #endif /* CONFIG_SPD_EEPROM */
400 memctl->memc_psrt = psrt;
401 memctl->memc_or2 = or;
402 memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;
403 ramaddr = (uchar *) CFG_SDRAM_BASE;
404 memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */
406 memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */
407 for (i = 0; i < 8; i++)
410 memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */
412 memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */
416 /* return total ram size of DIMM */
417 return (msize * 1024 * 1024);
420 int checkboard (void)
422 puts ("Board: Motorola MPC8260ADS\n");