2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
5 * This files is mostly identical to the original from
6 * board/freescale/mpc8308rdb/sdram.c
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/bitops.h>
33 #include <asm/processor.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 /* Fixed sdram init -- doesn't use serial presence detect.
39 * This is useful for faster booting in configs where the RAM is unlikely
40 * to be changed, or for things like NAND booting where space is tight.
42 static long fixed_sdram(void)
44 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
45 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
46 u32 msize_log2 = __ilog2(msize);
48 out_be32(&im->sysconf.ddrlaw[0].bar,
49 CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
50 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
51 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
53 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
54 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
56 /* Currently we use only one CS, so disable the other bank. */
57 out_be32(&im->ddr.cs_config[1], 0);
59 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
60 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
61 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
62 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
63 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
65 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
66 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
67 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
68 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
70 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
73 /* enable DDR controller */
74 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
77 return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
80 phys_size_t initdram(int board_type)
82 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
85 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
89 msize = fixed_sdram();
91 /* return total bus SDRAM size(bytes) -- DDR */