2 * Copyright Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * 20050101: Eran Liberty (liberty@freescale.com)
24 * Initial file creating (porting from 85XX & 8260)
30 #include <asm/mpc8349_pci.h>
34 #if defined(CONFIG_PCI)
37 #if defined(CONFIG_SPD_EEPROM)
38 #include <spd_sdram.h>
40 int fixed_sdram(void);
41 void sdram_init(void);
43 int board_early_init_f (void)
45 volatile u8* bcsr = (volatile u8*)CFG_BCSR;
47 /* Enable flash write */
54 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
56 long int initdram (int board_type)
58 volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
61 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
64 /* DDR SDRAM - Main SODIMM */
65 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
66 #if defined(CONFIG_SPD_EEPROM)
67 msize = spd_sdram(NULL);
69 msize = fixed_sdram();
72 * Initialize SDRAM if it is on local bus.
76 /* return total bus SDRAM size(bytes) -- DDR */
77 return (msize * 1024 * 1024);
81 #if !defined(CONFIG_SPD_EEPROM)
82 /*************************************************************************
83 * fixed sdram init -- doesn't use serial presence detect.
84 ************************************************************************/
87 volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
93 for (ddr_size = msize << 20, ddr_size_log2 = 0;
95 ddr_size = ddr_size>>1, ddr_size_log2++) {
100 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
101 #if (CFG_DDR_SIZE != 256)
102 #warning Currenly any ddr size other than 256 is not supported
105 im->ddr.csbnds[0].csbnds = 0x00100017;
106 im->ddr.csbnds[1].csbnds = 0x0018001f;
107 im->ddr.csbnds[2].csbnds = 0x00000007;
108 im->ddr.csbnds[3].csbnds = 0x0008000f;
109 im->ddr.cs_config[0] = CFG_DDR_CONFIG;
110 im->ddr.cs_config[1] = CFG_DDR_CONFIG;
111 im->ddr.cs_config[2] = CFG_DDR_CONFIG;
112 im->ddr.cs_config[3] = CFG_DDR_CONFIG;
113 im->ddr.timing_cfg_1 =
114 3 << TIMING_CFG1_PRETOACT_SHIFT |
115 7 << TIMING_CFG1_ACTTOPRE_SHIFT |
116 3 << TIMING_CFG1_ACTTORW_SHIFT |
117 4 << TIMING_CFG1_CASLAT_SHIFT |
118 3 << TIMING_CFG1_REFREC_SHIFT |
119 3 << TIMING_CFG1_WRREC_SHIFT |
120 2 << TIMING_CFG1_ACTTOACT_SHIFT |
121 1 << TIMING_CFG1_WRTORD_SHIFT;
122 im->ddr.timing_cfg_2 = 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT;
125 #if defined(CONFIG_DDR_2T_TIMING)
128 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
130 0x2000 << SDRAM_MODE_ESD_SHIFT |
131 0x0162 << SDRAM_MODE_SD_SHIFT;
133 im->ddr.sdram_interval = 0x045B << SDRAM_INTERVAL_REFINT_SHIFT |
134 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT;
137 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
141 #endif/*!CFG_SPD_EEPROM*/
144 int checkboard (void)
146 puts("Board: Freescale MPC8349ADS\n");
150 #if defined(CONFIG_PCI)
152 * Initialize PCI Devices, report devices found
154 #ifndef CONFIG_PCI_PNP
155 static struct pci_config_table pci_mpc83xxads_config_table[] = {
156 {PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,
157 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
159 PCI_COMMON_MEMORY | PCI_COMMAND_MASTER
166 volatile static struct pci_controller hose[] = {
168 #ifndef CONFIG_PCI_PNP
169 config_table:pci_mpc83xxads_config_table,
173 #ifndef CONFIG_PCI_PNP
174 config_table:pci_mpc83xxads_config_table,
178 #endif /* CONFIG_PCI */
185 extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
187 pci_mpc83xx_init(hose);
188 #endif /* CONFIG_PCI */
192 * if MPC8349ADS is soldered with SDRAM
194 #if defined(CFG_BR2_PRELIM) \
195 && defined(CFG_OR2_PRELIM) \
196 && defined(CFG_LBLAWBAR2_PRELIM) \
197 && defined(CFG_LBLAWAR2_PRELIM)
199 * Initialize SDRAM memory on the Local Bus.
205 volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
206 volatile lbus8349_t *lbc= &immap->lbus;
207 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
209 puts("\n SDRAM on Local Bus: ");
210 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
213 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
216 /*setup mtrpt, lsrt and lbcr for LB bus*/
217 lbc->lbcr = CFG_LBC_LBCR;
218 lbc->mrtpr = CFG_LBC_MRTPR;
219 lbc->lsrt = CFG_LBC_LSRT;
223 * Configure the SDRAM controller Machine Mode Register.
225 lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation*/
227 lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733;precharge all the banks*/
232 lbc->lsdmr = CFG_LBC_LSDMR_2;/*0x48636733;auto refresh*/
259 /* 0x58636733;mode register write operation */
260 lbc->lsdmr = CFG_LBC_LSDMR_4;
265 lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation*/
274 put("SDRAM on Local Bus is NOT available!\n");