2 * See file CREDITS for list of people who contributed to this
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/global_data.h>
26 #include <asm/mpc8349_pci.h>
31 /* System RAM mapped to PCI space */
32 #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
33 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
35 #ifndef CONFIG_PCI_PNP
36 static struct pci_config_table pci_mpc83xxads_config_table[] = {
37 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
38 PCI_IDSEL_NUMBER, PCI_ANY_ID,
39 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
41 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
48 static struct pci_controller pci_hose[] = {
50 #ifndef CONFIG_PCI_PNP
51 config_table:pci_mpc83xxads_config_table,
55 #ifndef CONFIG_PCI_PNP
56 config_table:pci_mpc83xxads_config_table,
61 /**************************************************************************
63 * pib_init() -- initialize the PCA9555PW IO expander on the PIB board
71 * Assign PIB PMC slot to desired PCI bus
73 mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
74 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
77 i2c_write(0x23, 0x6, 1, &val8, 1);
78 i2c_write(0x23, 0x7, 1, &val8, 1);
80 i2c_write(0x23, 0x2, 1, &val8, 1);
81 i2c_write(0x23, 0x3, 1, &val8, 1);
84 i2c_write(0x26, 0x6, 1, &val8, 1);
86 i2c_write(0x26, 0x7, 1, &val8, 1);
87 #if defined(PCI_64BIT)
88 val8 = 0xf4; /* PMC2:PCI1/64-bit */
89 #elif defined(PCI_ALL_PCI1)
90 val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
91 #elif defined(PCI_ONE_PCI1)
92 val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
94 val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
96 i2c_write(0x26, 0x2, 1, &val8, 1);
98 i2c_write(0x26, 0x3, 1, &val8, 1);
100 i2c_write(0x27, 0x6, 1, &val8, 1);
101 i2c_write(0x27, 0x7, 1, &val8, 1);
103 i2c_write(0x27, 0x2, 1, &val8, 1);
105 i2c_write(0x27, 0x3, 1, &val8, 1);
108 #if defined(PCI_64BIT)
109 printf("PCI1: 64-bit on PMC2\n");
110 #elif defined(PCI_ALL_PCI1)
111 printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
112 #elif defined(PCI_ONE_PCI1)
113 printf("PCI1: 32-bit on PMC1\n");
114 printf("PCI2: 32-bit on PMC2, PMC3\n");
116 printf("PCI1: 32-bit on PMC1, PMC2\n");
117 printf("PCI2: 32-bit on PMC3\n");
121 /**************************************************************************
124 * NOTICE: PCI2 is not currently supported
130 DECLARE_GLOBAL_DATA_PTR;
131 volatile immap_t * immr;
132 volatile clk8349_t * clk;
133 volatile law8349_t * pci_law;
134 volatile pot8349_t * pci_pot;
135 volatile pcictrl8349_t * pci_ctrl;
136 volatile pciconf8349_t * pci_conf;
140 struct pci_controller * hose;
142 immr = (immap_t *)CFG_IMMRBAR;
143 clk = (clk8349_t *)&immr->clk;
144 pci_law = immr->sysconf.pcilaw;
145 pci_pot = immr->ios.pot;
146 pci_ctrl = immr->pci_ctrl;
147 pci_conf = immr->pci_conf;
154 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
159 clk->occr = 0xff000000;
163 * Release PCI RST Output signal
169 #ifdef CONFIG_MPC83XX_PCI2
175 /* We need to wait at least a 1sec based on PCI specs */
179 for (i = 0; i < 1000; ++i)
184 * Configure PCI Local Access Windows
186 pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
187 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
189 pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
190 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
193 * Configure PCI Outbound Translation Windows
196 /* PCI1 mem space - prefetch */
197 pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
198 pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
199 pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
202 pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
203 pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
204 pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
206 /* PCI1 mmio - non-prefetch mem space */
207 pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
208 pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
209 pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
212 * Configure PCI Inbound Translation Windows
215 /* we need RAM mapped to PCI space for the devices to
216 * access main memory */
217 pci_ctrl[0].pitar1 = 0x0;
218 pci_ctrl[0].pibar1 = 0x0;
219 pci_ctrl[0].piebar1 = 0x0;
220 pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
222 hose->first_busno = 0;
223 hose->last_busno = 0xff;
225 /* PCI memory prefetch space */
226 pci_set_region(hose->regions + 0,
230 PCI_REGION_MEM|PCI_REGION_PREFETCH);
232 /* PCI memory space */
233 pci_set_region(hose->regions + 1,
240 pci_set_region(hose->regions + 2,
246 /* System memory space */
247 pci_set_region(hose->regions + 3,
248 CONFIG_PCI_SYS_MEM_BUS,
249 CONFIG_PCI_SYS_MEM_PHYS,
251 PCI_REGION_MEM | PCI_REGION_MEMORY);
253 hose->region_count = 4;
255 pci_setup_indirect(hose,
256 (CFG_IMMRBAR+0x8300),
257 (CFG_IMMRBAR+0x8304));
259 pci_register_hose(hose);
262 * Write to Command register
265 dev = PCI_BDF(hose->first_busno, 0, 0);
266 pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
267 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
268 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
271 * Clear non-reserved bits in status register.
273 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
274 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
275 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
277 #ifdef CONFIG_PCI_SCAN_SHOW
278 printf("PCI: Bus Dev VenId DevId Class Int\n");
283 hose->last_busno = pci_hose_scan(hose);
285 #ifdef CONFIG_MPC83XX_PCI2
289 * Configure PCI Outbound Translation Windows
292 /* PCI2 mem space - prefetch */
293 pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
294 pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
295 pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
298 pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
299 pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
300 pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
302 /* PCI2 mmio - non-prefetch mem space */
303 pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
304 pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
305 pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK);
308 * Configure PCI Inbound Translation Windows
311 /* we need RAM mapped to PCI space for the devices to
312 * access main memory */
313 pci_ctrl[1].pitar1 = 0x0;
314 pci_ctrl[1].pibar1 = 0x0;
315 pci_ctrl[1].piebar1 = 0x0;
316 pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
318 hose->first_busno = pci_hose[0].last_busno + 1;
319 hose->last_busno = 0xff;
321 /* PCI memory prefetch space */
322 pci_set_region(hose->regions + 0,
326 PCI_REGION_MEM|PCI_REGION_PREFETCH);
328 /* PCI memory space */
329 pci_set_region(hose->regions + 1,
336 pci_set_region(hose->regions + 2,
342 /* System memory space */
343 pci_set_region(hose->regions + 3,
344 CONFIG_PCI_SYS_MEM_BUS,
345 CONFIG_PCI_SYS_MEM_PHYS,
347 PCI_REGION_MEM | PCI_REGION_MEMORY);
349 hose->region_count = 4;
351 pci_setup_indirect(hose,
352 (CFG_IMMRBAR+0x8380),
353 (CFG_IMMRBAR+0x8384));
355 pci_register_hose(hose);
358 * Write to Command register
361 dev = PCI_BDF(hose->first_busno, 0, 0);
362 pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
363 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
364 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
367 * Clear non-reserved bits in status register.
369 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
370 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
371 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
376 hose->last_busno = pci_hose_scan(hose);
380 #endif /* CONFIG_PCI */