3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/mpc8349_pci.h>
33 #if defined(CONFIG_PCI)
36 #if defined(CONFIG_SPD_EEPROM)
37 #include <spd_sdram.h>
39 int fixed_sdram(void);
40 void sdram_init(void);
42 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
43 void ddr_enable_ecc(unsigned int dram_size);
46 int board_early_init_f (void)
48 volatile u8* bcsr = (volatile u8*)CFG_BCSR;
50 /* Enable flash write */
56 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
58 long int initdram (int board_type)
60 volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
63 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
66 puts("Initializing\n");
68 /* DDR SDRAM - Main SODIMM */
69 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
70 #if defined(CONFIG_SPD_EEPROM)
73 msize = fixed_sdram();
76 * Initialize SDRAM if it is on local bus.
80 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
82 * Initialize and enable DDR ECC.
84 ddr_enable_ecc(msize * 1024 * 1024);
87 /* return total bus SDRAM size(bytes) -- DDR */
88 return (msize * 1024 * 1024);
91 #if !defined(CONFIG_SPD_EEPROM)
92 /*************************************************************************
93 * fixed sdram init -- doesn't use serial presence detect.
94 ************************************************************************/
97 volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
102 msize = CFG_DDR_SIZE;
103 for (ddr_size = msize << 20, ddr_size_log2 = 0;
105 ddr_size = ddr_size>>1, ddr_size_log2++) {
110 im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
111 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
113 #if (CFG_DDR_SIZE != 256)
114 #warning Currenly any ddr size other than 256 is not supported
116 im->ddr.csbnds[2].csbnds = 0x0000000f;
117 im->ddr.cs_config[2] = CFG_DDR_CONFIG;
119 /* currently we use only one CS, so disable the other banks */
120 im->ddr.cs_config[0] = 0;
121 im->ddr.cs_config[1] = 0;
122 im->ddr.cs_config[3] = 0;
124 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
125 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
129 #if defined(CONFIG_DDR_2T_TIMING)
132 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
133 #if defined (CONFIG_DDR_32BIT)
134 /* for 32-bit mode burst length is 8 */
135 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
137 im->ddr.sdram_mode = CFG_DDR_MODE;
139 im->ddr.sdram_interval = CFG_DDR_INTERVAL;
142 /* enable DDR controller */
143 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
146 #endif/*!CFG_SPD_EEPROM*/
149 int checkboard (void)
151 puts("Board: Freescale MPC8349EMDS\n");
155 #if defined(CONFIG_PCI)
157 * Initialize PCI Devices, report devices found
159 #ifndef CONFIG_PCI_PNP
160 static struct pci_config_table pci_mpc8349emds_config_table[] = {
161 {PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,
162 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
164 PCI_COMMON_MEMORY | PCI_COMMAND_MASTER
170 volatile static struct pci_controller hose[] = {
172 #ifndef CONFIG_PCI_PNP
173 config_table:pci_mpc8349emds_config_table,
177 #ifndef CONFIG_PCI_PNP
178 config_table:pci_mpc8349emds_config_table,
182 #endif /* CONFIG_PCI */
184 void pci_init_board(void)
187 extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
189 pci_mpc83xx_init(hose);
190 #endif /* CONFIG_PCI */
194 * if MPC8349EMDS is soldered with SDRAM
196 #if defined(CFG_BR2_PRELIM) \
197 && defined(CFG_OR2_PRELIM) \
198 && defined(CFG_LBLAWBAR2_PRELIM) \
199 && defined(CFG_LBLAWAR2_PRELIM)
201 * Initialize SDRAM memory on the Local Bus.
204 void sdram_init(void)
206 volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
207 volatile lbus8349_t *lbc= &immap->lbus;
208 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
210 puts("\n SDRAM on Local Bus: ");
211 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
214 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
217 /* setup mtrpt, lsrt and lbcr for LB bus */
218 lbc->lbcr = CFG_LBC_LBCR;
219 lbc->mrtpr = CFG_LBC_MRTPR;
220 lbc->lsrt = CFG_LBC_LSRT;
224 * Configure the SDRAM controller Machine Mode Register.
226 lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
228 lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
233 lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
260 /* 0x58636733; mode register write operation */
261 lbc->lsdmr = CFG_LBC_LSDMR_4;
266 lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
272 void sdram_init(void)
274 put("SDRAM on Local Bus is NOT available!\n");
278 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
282 void ecc_print_status(void)
284 volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
285 volatile ddr8349_t *ddr = &immap->ddr;
287 printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
290 printf("Memory Error Interrupt Enable:\n");
291 printf(" Multiple-Bit Error Interrupt Enable: %d\n",
292 (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
293 printf(" Single-Bit Error Interrupt Enable: %d\n",
294 (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
295 printf(" Memory Select Error Interrupt Enable: %d\n\n",
296 (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
299 printf("Memory Error Disable:\n");
300 printf(" Multiple-Bit Error Disable: %d\n",
301 (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
302 printf(" Sinle-Bit Error Disable: %d\n",
303 (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
304 printf(" Memory Select Error Disable: %d\n\n",
305 (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
307 /* Error injection */
308 printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
309 ddr->data_err_inject_hi, ddr->data_err_inject_lo);
311 printf("Memory Data Path Error Injection Mask ECC:\n");
312 printf(" ECC Mirror Byte: %d\n",
313 (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
314 printf(" ECC Injection Enable: %d\n",
315 (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
316 printf(" ECC Error Injection Mask: 0x%02x\n\n",
317 ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
319 /* SBE counter/threshold */
320 printf("Memory Single-Bit Error Management (0..255):\n");
321 printf(" Single-Bit Error Threshold: %d\n",
322 (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
323 printf(" Single-Bit Error Counter: %d\n\n",
324 (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
327 printf("Memory Error Detect:\n");
328 printf(" Multiple Memory Errors: %d\n",
329 (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
330 printf(" Multiple-Bit Error: %d\n",
331 (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
332 printf(" Single-Bit Error: %d\n",
333 (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
334 printf(" Memory Select Error: %d\n\n",
335 (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
338 printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
339 printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
340 ddr->capture_data_hi, ddr->capture_data_lo);
341 printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
342 ddr->capture_ecc & CAPTURE_ECC_ECE);
344 printf("Memory Error Attributes Capture:\n");
345 printf(" Data Beat Number: %d\n",
346 (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT);
347 printf(" Transaction Size: %d\n",
348 (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT);
349 printf(" Transaction Source: %d\n",
350 (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT);
351 printf(" Transaction Type: %d\n",
352 (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT);
353 printf(" Error Information Valid: %d\n\n",
354 ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
357 int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
359 volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
360 volatile ddr8349_t *ddr = &immap->ddr;
362 u64 *addr, count, val64;
366 printf ("Usage:\n%s\n", cmdtp->usage);
371 if (strcmp(argv[1], "status") == 0) {
374 } else if (strcmp(argv[1], "captureclear") == 0) {
375 ddr->capture_address = 0;
376 ddr->capture_data_hi = 0;
377 ddr->capture_data_lo = 0;
378 ddr->capture_ecc = 0;
379 ddr->capture_attributes = 0;
385 if (strcmp(argv[1], "sbecnt") == 0) {
386 val = simple_strtoul(argv[2], NULL, 10);
388 printf("Incorrect Counter value, should be 0..255\n");
392 val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
393 val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
397 } else if (strcmp(argv[1], "sbethr") == 0) {
398 val = simple_strtoul(argv[2], NULL, 10);
400 printf("Incorrect Counter value, should be 0..255\n");
404 val = (val << ECC_ERROR_MAN_SBET_SHIFT);
405 val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
409 } else if (strcmp(argv[1], "errdisable") == 0) {
410 val = ddr->err_disable;
412 if (strcmp(argv[2], "+sbe") == 0) {
413 val |= ECC_ERROR_DISABLE_SBED;
414 } else if (strcmp(argv[2], "+mbe") == 0) {
415 val |= ECC_ERROR_DISABLE_MBED;
416 } else if (strcmp(argv[2], "+mse") == 0) {
417 val |= ECC_ERROR_DISABLE_MSED;
418 } else if (strcmp(argv[2], "+all") == 0) {
419 val |= (ECC_ERROR_DISABLE_SBED |
420 ECC_ERROR_DISABLE_MBED |
421 ECC_ERROR_DISABLE_MSED);
422 } else if (strcmp(argv[2], "-sbe") == 0) {
423 val &= ~ECC_ERROR_DISABLE_SBED;
424 } else if (strcmp(argv[2], "-mbe") == 0) {
425 val &= ~ECC_ERROR_DISABLE_MBED;
426 } else if (strcmp(argv[2], "-mse") == 0) {
427 val &= ~ECC_ERROR_DISABLE_MSED;
428 } else if (strcmp(argv[2], "-all") == 0) {
429 val &= ~(ECC_ERROR_DISABLE_SBED |
430 ECC_ERROR_DISABLE_MBED |
431 ECC_ERROR_DISABLE_MSED);
433 printf("Incorrect err_disable field\n");
437 ddr->err_disable = val;
438 __asm__ __volatile__ ("sync");
439 __asm__ __volatile__ ("isync");
441 } else if (strcmp(argv[1], "errdetectclr") == 0) {
442 val = ddr->err_detect;
444 if (strcmp(argv[2], "mme") == 0) {
445 val |= ECC_ERROR_DETECT_MME;
446 } else if (strcmp(argv[2], "sbe") == 0) {
447 val |= ECC_ERROR_DETECT_SBE;
448 } else if (strcmp(argv[2], "mbe") == 0) {
449 val |= ECC_ERROR_DETECT_MBE;
450 } else if (strcmp(argv[2], "mse") == 0) {
451 val |= ECC_ERROR_DETECT_MSE;
452 } else if (strcmp(argv[2], "all") == 0) {
453 val |= (ECC_ERROR_DETECT_MME |
454 ECC_ERROR_DETECT_MBE |
455 ECC_ERROR_DETECT_SBE |
456 ECC_ERROR_DETECT_MSE);
458 printf("Incorrect err_detect field\n");
462 ddr->err_detect = val;
464 } else if (strcmp(argv[1], "injectdatahi") == 0) {
465 val = simple_strtoul(argv[2], NULL, 16);
467 ddr->data_err_inject_hi = val;
469 } else if (strcmp(argv[1], "injectdatalo") == 0) {
470 val = simple_strtoul(argv[2], NULL, 16);
472 ddr->data_err_inject_lo = val;
474 } else if (strcmp(argv[1], "injectecc") == 0) {
475 val = simple_strtoul(argv[2], NULL, 16);
477 printf("Incorrect ECC inject mask, should be 0x00..0xff\n");
480 val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
482 ddr->ecc_err_inject = val;
484 } else if (strcmp(argv[1], "inject") == 0) {
485 val = ddr->ecc_err_inject;
487 if (strcmp(argv[2], "en") == 0)
488 val |= ECC_ERR_INJECT_EIEN;
489 else if (strcmp(argv[2], "dis") == 0)
490 val &= ~ECC_ERR_INJECT_EIEN;
492 printf("Incorrect command\n");
494 ddr->ecc_err_inject = val;
495 __asm__ __volatile__ ("sync");
496 __asm__ __volatile__ ("isync");
498 } else if (strcmp(argv[1], "mirror") == 0) {
499 val = ddr->ecc_err_inject;
501 if (strcmp(argv[2], "en") == 0)
502 val |= ECC_ERR_INJECT_EMB;
503 else if (strcmp(argv[2], "dis") == 0)
504 val &= ~ECC_ERR_INJECT_EMB;
506 printf("Incorrect command\n");
508 ddr->ecc_err_inject = val;
514 if (strcmp(argv[1], "test") == 0) {
515 addr = (u64 *)simple_strtoul(argv[2], NULL, 16);
516 count = simple_strtoul(argv[3], NULL, 16);
519 printf("Address not alligned on double word boundary\n");
523 disable_interrupts();
526 for (i = addr; i < addr + count; i++) {
528 ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
529 __asm__ __volatile__ ("sync");
530 __asm__ __volatile__ ("isync");
532 /* write memory location injecting errors */
533 *i = 0x1122334455667788ULL;
534 __asm__ __volatile__ ("sync");
536 /* disable injects */
537 ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
538 __asm__ __volatile__ ("sync");
539 __asm__ __volatile__ ("isync");
541 /* read data, this generates ECC error */
543 __asm__ __volatile__ ("sync");
545 /* disable errors for ECC */
546 ddr->err_disable |= ~ECC_ERROR_ENABLE;
547 __asm__ __volatile__ ("sync");
548 __asm__ __volatile__ ("isync");
550 /* re-initialize memory, write the location again
551 * NOT injecting errors this time */
552 *i = 0xcafecafecafecafeULL;
553 __asm__ __volatile__ ("sync");
555 /* enable errors for ECC */
556 ddr->err_disable &= ECC_ERROR_ENABLE;
557 __asm__ __volatile__ ("sync");
558 __asm__ __volatile__ ("isync");
568 printf ("Usage:\n%s\n", cmdtp->usage);
574 "ecc - support for DDR ECC features\n",
575 "status - print out status info\n"
576 "ecc captureclear - clear capture regs data\n"
577 "ecc sbecnt <val> - set Single-Bit Error counter\n"
578 "ecc sbethr <val> - set Single-Bit Threshold\n"
579 "ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n"
580 " [-|+]sbe - Single-Bit Error\n"
581 " [-|+]mbe - Multiple-Bit Error\n"
582 " [-|+]mse - Memory Select Error\n"
583 " [-|+]all - all errors\n"
584 "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
585 " mme - Multiple Memory Errors\n"
586 " sbe - Single-Bit Error\n"
587 " mbe - Multiple-Bit Error\n"
588 " mse - Memory Select Error\n"
589 " all - all errors\n"
590 "ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n"
591 "ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n"
592 "ecc injectecc <ecc> - set ECC Error Injection Mask\n"
593 "ecc inject <en|dis> - enable/disable error injection\n"
594 "ecc mirror <en|dis> - enable/disable mirror byte\n"
595 "ecc test <addr> <cnt> - test mem region:\n"
596 " - enables injects\n"
597 " - writes pattern injecting errors\n"
598 " - disables injects\n"
599 " - reads pattern back, generates error\n"
602 #endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */