git.sur5r.net Git - u-boot/blob - board/mpc8349emds/mpc8349emds.c

   1 /*
   2  * (C) Copyright 2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  */
  24
  25 #include <common.h>
  26 #include <ioports.h>
  27 #include <mpc83xx.h>
  28 #include <asm/mpc8349_pci.h>
  29 #include <i2c.h>
  30 #include <spd.h>
  31 #include <miiphy.h>
  32 #include <command.h>
  33 #if defined(CONFIG_PCI)
  34 #include <pci.h>
  35 #endif
  36 #if defined(CONFIG_SPD_EEPROM)
  37 #include <spd_sdram.h>
  38 #endif
  39 int fixed_sdram(void);
  40 void sdram_init(void);
  41
  42 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
  43 void ddr_enable_ecc(unsigned int dram_size);
  44 #endif
  45
  46 int board_early_init_f (void)
  47 {
  48         volatile u8* bcsr = (volatile u8*)CFG_BCSR;
  49
  50         /* Enable flash write */
  51         bcsr[1] &= ~0x01;
  52
  53         return 0;
  54 }
  55
  56 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
  57
  58 long int initdram (int board_type)
  59 {
  60         volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
  61         u32 msize = 0;
  62
  63         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
  64                 return -1;
  65
  66         /* DDR SDRAM - Main SODIMM */
  67         im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
  68 #if defined(CONFIG_SPD_EEPROM)
  69
  70         msize = spd_sdram(0);
  71 #else
  72         msize = fixed_sdram();
  73 #endif
  74         /*
  75          * Initialize SDRAM if it is on local bus.
  76          */
  77         sdram_init();
  78
  79 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  80         /*
  81          * Initialize and enable DDR ECC.
  82          */
  83         ddr_enable_ecc(msize * 1024 * 1024);
  84 #endif
  85         puts("   DDR RAM: ");
  86         /* return total bus SDRAM size(bytes)  -- DDR */
  87         return (msize * 1024 * 1024);
  88 }
  89
  90 #if !defined(CONFIG_SPD_EEPROM)
  91 /*************************************************************************
  92  *  fixed sdram init -- doesn't use serial presence detect.
  93  ************************************************************************/
  94 int fixed_sdram(void)
  95 {
  96         volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
  97         u32 msize = 0;
  98         u32 ddr_size;
  99         u32 ddr_size_log2;
 100
 101         msize = CFG_DDR_SIZE;
 102         for (ddr_size = msize << 20, ddr_size_log2 = 0;
 103              (ddr_size > 1);
 104              ddr_size = ddr_size>>1, ddr_size_log2++) {
 105                 if (ddr_size & 1) {
 106                         return -1;
 107                 }
 108         }
 109         im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 110 #if (CFG_DDR_SIZE != 256)
 111 #warning Currenly any ddr size other than 256 is not supported
 112 #endif
 113
 114         im->ddr.csbnds[0].csbnds = 0x00100017;
 115         im->ddr.csbnds[1].csbnds = 0x0018001f;
 116         im->ddr.csbnds[2].csbnds = 0x00000007;
 117         im->ddr.csbnds[3].csbnds = 0x0008000f;
 118         im->ddr.cs_config[0] = CFG_DDR_CONFIG;
 119         im->ddr.cs_config[1] = CFG_DDR_CONFIG;
 120         im->ddr.cs_config[2] = CFG_DDR_CONFIG;
 121         im->ddr.cs_config[3] = CFG_DDR_CONFIG;
 122         im->ddr.timing_cfg_1 =
 123                 3 << TIMING_CFG1_PRETOACT_SHIFT |
 124                 7 << TIMING_CFG1_ACTTOPRE_SHIFT |
 125                 3 << TIMING_CFG1_ACTTORW_SHIFT  |
 126                 4 << TIMING_CFG1_CASLAT_SHIFT   |
 127                 3 << TIMING_CFG1_REFREC_SHIFT   |
 128                 3 << TIMING_CFG1_WRREC_SHIFT    |
 129                 2 << TIMING_CFG1_ACTTOACT_SHIFT |
 130                 1 << TIMING_CFG1_WRTORD_SHIFT;
 131         im->ddr.timing_cfg_2 = 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT;
 132         im->ddr.sdram_cfg =
 133                 SDRAM_CFG_SREN
 134 #if defined(CONFIG_DDR_2T_TIMING)
 135                 | SDRAM_CFG_2T_EN
 136 #endif
 137                 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
 138         im->ddr.sdram_mode =
 139                 0x2000 << SDRAM_MODE_ESD_SHIFT |
 140                 0x0162 << SDRAM_MODE_SD_SHIFT;
 141
 142         im->ddr.sdram_interval = 0x045B << SDRAM_INTERVAL_REFINT_SHIFT |
 143                 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT;
 144         udelay(200);
 145
 146         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 147
 148         return msize;
 149 }
 150 #endif/*!CFG_SPD_EEPROM*/
 151
 152
 153 int checkboard (void)
 154 {
 155         puts("Board: Freescale MPC8349EMDS\n");
 156         return 0;
 157 }
 158
 159 #if defined(CONFIG_PCI)
 160 /*
 161  * Initialize PCI Devices, report devices found
 162  */
 163 #ifndef CONFIG_PCI_PNP
 164 static struct pci_config_table pci_mpc8349emds_config_table[] = {
 165         {PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,
 166         pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
 167                                     PCI_ENET0_MEMADDR,
 168                                     PCI_COMMON_MEMORY | PCI_COMMAND_MASTER
 169         } },
 170         {}
 171 }
 172 #endif
 173
 174 volatile static struct pci_controller hose[] = {
 175         {
 176 #ifndef CONFIG_PCI_PNP
 177         config_table:pci_mpc8349emds_config_table,
 178 #endif
 179         },
 180         {
 181 #ifndef CONFIG_PCI_PNP
 182         config_table:pci_mpc8349emds_config_table,
 183 #endif
 184         }
 185 };
 186 #endif /* CONFIG_PCI */
 187
 188 void pci_init_board(void)
 189 {
 190 #ifdef CONFIG_PCI
 191         extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
 192
 193         pci_mpc83xx_init(hose);
 194 #endif /* CONFIG_PCI */
 195 }
 196
 197 /*
 198  * if MPC8349EMDS is soldered with SDRAM
 199  */
 200 #if defined(CFG_BR2_PRELIM)  \
 201         && defined(CFG_OR2_PRELIM) \
 202         && defined(CFG_LBLAWBAR2_PRELIM) \
 203         && defined(CFG_LBLAWAR2_PRELIM)
 204 /*
 205  * Initialize SDRAM memory on the Local Bus.
 206  */
 207
 208 void sdram_init(void)
 209 {
 210         volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
 211         volatile lbus8349_t *lbc= &immap->lbus;
 212         uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 213
 214         puts("\n   SDRAM on Local Bus: ");
 215         print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 216
 217         /*
 218          * Setup SDRAM Base and Option Registers, already done in cpu_init.c
 219          */
 220
 221         /* setup mtrpt, lsrt and lbcr for LB bus */
 222         lbc->lbcr = CFG_LBC_LBCR;
 223         lbc->mrtpr = CFG_LBC_MRTPR;
 224         lbc->lsrt = CFG_LBC_LSRT;
 225         asm("sync");
 226
 227         /*
 228          * Configure the SDRAM controller Machine Mode Register.
 229          */
 230         lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
 231
 232         lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
 233         asm("sync");
 234         *sdram_addr = 0xff;
 235         udelay(100);
 236
 237         lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
 238         asm("sync");
 239         /*1 times*/
 240         *sdram_addr = 0xff;
 241         udelay(100);
 242         /*2 times*/
 243         *sdram_addr = 0xff;
 244         udelay(100);
 245         /*3 times*/
 246         *sdram_addr = 0xff;
 247         udelay(100);
 248         /*4 times*/
 249         *sdram_addr = 0xff;
 250         udelay(100);
 251         /*5 times*/
 252         *sdram_addr = 0xff;
 253         udelay(100);
 254         /*6 times*/
 255         *sdram_addr = 0xff;
 256         udelay(100);
 257         /*7 times*/
 258         *sdram_addr = 0xff;
 259         udelay(100);
 260         /*8 times*/
 261         *sdram_addr = 0xff;
 262         udelay(100);
 263
 264         /* 0x58636733; mode register write operation */
 265         lbc->lsdmr = CFG_LBC_LSDMR_4;
 266         asm("sync");
 267         *sdram_addr = 0xff;
 268         udelay(100);
 269
 270         lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
 271         asm("sync");
 272         *sdram_addr = 0xff;
 273         udelay(100);
 274 }
 275 #else
 276 void sdram_init(void)
 277 {
 278         put("SDRAM on Local Bus is NOT available!\n");
 279 }
 280 #endif
 281
 282 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
 283 /*
 284  * ECC user commands
 285  */
 286 void ecc_print_status(void)
 287 {
 288         volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
 289         volatile ddr8349_t *ddr = &immap->ddr;
 290
 291         printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
 292
 293         /* Interrupts */
 294         printf("Memory Error Interrupt Enable:\n");
 295         printf("  Multiple-Bit Error Interrupt Enable: %d\n",
 296                         (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
 297         printf("  Single-Bit Error Interrupt Enable: %d\n",
 298                         (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
 299         printf("  Memory Select Error Interrupt Enable: %d\n\n",
 300                         (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
 301
 302         /* Error disable */
 303         printf("Memory Error Disable:\n");
 304         printf("  Multiple-Bit Error Disable: %d\n",
 305                         (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
 306         printf("  Sinle-Bit Error Disable: %d\n",
 307                         (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
 308         printf("  Memory Select Error Disable: %d\n\n",
 309                         (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
 310
 311         /* Error injection */
 312         printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
 313                         ddr->data_err_inject_hi, ddr->data_err_inject_lo);
 314
 315         printf("Memory Data Path Error Injection Mask ECC:\n");
 316         printf("  ECC Mirror Byte: %d\n",
 317                         (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
 318         printf("  ECC Injection Enable: %d\n",
 319                         (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
 320         printf("  ECC Error Injection Mask: 0x%02x\n\n",
 321                         ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
 322
 323         /* SBE counter/threshold */
 324         printf("Memory Single-Bit Error Management (0..255):\n");
 325         printf("  Single-Bit Error Threshold: %d\n",
 326                         (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
 327         printf("  Single-Bit Error Counter: %d\n\n",
 328                         (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
 329
 330         /* Error detect */
 331         printf("Memory Error Detect:\n");
 332         printf("  Multiple Memory Errors: %d\n",
 333                         (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
 334         printf("  Multiple-Bit Error: %d\n",
 335                         (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
 336         printf("  Single-Bit Error: %d\n",
 337                         (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
 338         printf("  Memory Select Error: %d\n\n",
 339                         (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
 340
 341         /* Capture data */
 342         printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
 343         printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
 344                         ddr->capture_data_hi, ddr->capture_data_lo);
 345         printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
 346                 ddr->capture_ecc & CAPTURE_ECC_ECE);
 347
 348         printf("Memory Error Attributes Capture:\n");
 349         printf("  Data Beat Number: %d\n",
 350                         (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT);
 351         printf("  Transaction Size: %d\n",
 352                         (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT);
 353         printf("  Transaction Source: %d\n",
 354                         (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT);
 355         printf("  Transaction Type: %d\n",
 356                         (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT);
 357         printf("  Error Information Valid: %d\n\n",
 358                         ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
 359 }
 360
 361 int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 362 {
 363         volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
 364         volatile ddr8349_t *ddr = &immap->ddr;
 365         volatile u32 val;
 366         u64 *addr, count, val64;
 367         register u64 *i;
 368
 369         if (argc > 4) {
 370                 printf ("Usage:\n%s\n", cmdtp->usage);
 371                 return 1;
 372         }
 373
 374         if (argc == 2) {
 375                 if (strcmp(argv[1], "status") == 0) {
 376                         ecc_print_status();
 377                         return 0;
 378                 } else if (strcmp(argv[1], "captureclear") == 0) {
 379                         ddr->capture_address = 0;
 380                         ddr->capture_data_hi = 0;
 381                         ddr->capture_data_lo = 0;
 382                         ddr->capture_ecc = 0;
 383                         ddr->capture_attributes = 0;
 384                         return 0;
 385                 }
 386         }
 387
 388         if (argc == 3) {
 389                 if (strcmp(argv[1], "sbecnt") == 0) {
 390                         val = simple_strtoul(argv[2], NULL, 10);
 391                         if (val > 255) {
 392                                 printf("Incorrect Counter value, should be 0..255\n");
 393                                 return 1;
 394                         }
 395
 396                         val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
 397                         val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
 398
 399                         ddr->err_sbe = val;
 400                         return 0;
 401                 } else if (strcmp(argv[1], "sbethr") == 0) {
 402                         val = simple_strtoul(argv[2], NULL, 10);
 403                         if (val > 255) {
 404                                 printf("Incorrect Counter value, should be 0..255\n");
 405                                 return 1;
 406                         }
 407
 408                         val = (val << ECC_ERROR_MAN_SBET_SHIFT);
 409                         val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
 410
 411                         ddr->err_sbe = val;
 412                         return 0;
 413                 } else if (strcmp(argv[1], "errdisable") == 0) {
 414                         val = ddr->err_disable;
 415
 416                         if (strcmp(argv[2], "+sbe") == 0) {
 417                                 val |= ECC_ERROR_DISABLE_SBED;
 418                         } else if (strcmp(argv[2], "+mbe") == 0) {
 419                                 val |= ECC_ERROR_DISABLE_MBED;
 420                         } else if (strcmp(argv[2], "+mse") == 0) {
 421                                 val |= ECC_ERROR_DISABLE_MSED;
 422                         } else if (strcmp(argv[2], "+all") == 0) {
 423                                 val |= (ECC_ERROR_DISABLE_SBED |
 424                                         ECC_ERROR_DISABLE_MBED |
 425                                         ECC_ERROR_DISABLE_MSED);
 426                         } else if (strcmp(argv[2], "-sbe") == 0) {
 427                                 val &= ~ECC_ERROR_DISABLE_SBED;
 428                         } else if (strcmp(argv[2], "-mbe") == 0) {
 429                                 val &= ~ECC_ERROR_DISABLE_MBED;
 430                         } else if (strcmp(argv[2], "-mse") == 0) {
 431                                 val &= ~ECC_ERROR_DISABLE_MSED;
 432                         } else if (strcmp(argv[2], "-all") == 0) {
 433                                 val &= ~(ECC_ERROR_DISABLE_SBED |
 434                                         ECC_ERROR_DISABLE_MBED |
 435                                         ECC_ERROR_DISABLE_MSED);
 436                         } else {
 437                                 printf("Incorrect err_disable field\n");
 438                                 return 1;
 439                         }
 440
 441                         ddr->err_disable = val;
 442                         __asm__ __volatile__ ("sync");
 443                         __asm__ __volatile__ ("isync");
 444                         return 0;
 445                 } else if (strcmp(argv[1], "errdetectclr") == 0) {
 446                         val = ddr->err_detect;
 447
 448                         if (strcmp(argv[2], "mme") == 0) {
 449                                 val |= ECC_ERROR_DETECT_MME;
 450                         } else if (strcmp(argv[2], "sbe") == 0) {
 451                                 val |= ECC_ERROR_DETECT_SBE;
 452                         } else if (strcmp(argv[2], "mbe") == 0) {
 453                                 val |= ECC_ERROR_DETECT_MBE;
 454                         } else if (strcmp(argv[2], "mse") == 0) {
 455                                 val |= ECC_ERROR_DETECT_MSE;
 456                         } else if (strcmp(argv[2], "all") == 0) {
 457                                 val |= (ECC_ERROR_DETECT_MME |
 458                                         ECC_ERROR_DETECT_MBE |
 459                                         ECC_ERROR_DETECT_SBE |
 460                                         ECC_ERROR_DETECT_MSE);
 461                         } else {
 462                                 printf("Incorrect err_detect field\n");
 463                                 return 1;
 464                         }
 465
 466                         ddr->err_detect = val;
 467                         return 0;
 468                 } else if (strcmp(argv[1], "injectdatahi") == 0) {
 469                         val = simple_strtoul(argv[2], NULL, 16);
 470
 471                         ddr->data_err_inject_hi = val;
 472                         return 0;
 473                 } else if (strcmp(argv[1], "injectdatalo") == 0) {
 474                         val = simple_strtoul(argv[2], NULL, 16);
 475
 476                         ddr->data_err_inject_lo = val;
 477                         return 0;
 478                 } else if (strcmp(argv[1], "injectecc") == 0) {
 479                         val = simple_strtoul(argv[2], NULL, 16);
 480                         if (val > 0xff) {
 481                                 printf("Incorrect ECC inject mask, should be 0x00..0xff\n");
 482                                 return 1;
 483                         }
 484                         val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
 485
 486                         ddr->ecc_err_inject = val;
 487                         return 0;
 488                 } else if (strcmp(argv[1], "inject") == 0) {
 489                         val = ddr->ecc_err_inject;
 490
 491                         if (strcmp(argv[2], "en") == 0)
 492                                 val |= ECC_ERR_INJECT_EIEN;
 493                         else if (strcmp(argv[2], "dis") == 0)
 494                                 val &= ~ECC_ERR_INJECT_EIEN;
 495                         else
 496                                 printf("Incorrect command\n");
 497
 498                         ddr->ecc_err_inject = val;
 499                         __asm__ __volatile__ ("sync");
 500                         __asm__ __volatile__ ("isync");
 501                         return 0;
 502                 } else if (strcmp(argv[1], "mirror") == 0) {
 503                         val = ddr->ecc_err_inject;
 504
 505                         if (strcmp(argv[2], "en") == 0)
 506                                 val |= ECC_ERR_INJECT_EMB;
 507                         else if (strcmp(argv[2], "dis") == 0)
 508                                 val &= ~ECC_ERR_INJECT_EMB;
 509                         else
 510                                 printf("Incorrect command\n");
 511
 512                         ddr->ecc_err_inject = val;
 513                         return 0;
 514                 }
 515         }
 516
 517         if (argc == 4) {
 518                 if (strcmp(argv[1], "test") == 0) {
 519                         addr = (u64 *)simple_strtoul(argv[2], NULL, 16);
 520                         count = simple_strtoul(argv[3], NULL, 16);
 521
 522                         if ((u32)addr % 8) {
 523                                 printf("Address not alligned on double word boundary\n");
 524                                 return 1;
 525                         }
 526
 527                         disable_interrupts();
 528                         icache_disable();
 529
 530                         for (i = addr; i < addr + count; i++) {
 531                                 /* enable injects */
 532                                 ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
 533                                 __asm__ __volatile__ ("sync");
 534                                 __asm__ __volatile__ ("isync");
 535
 536                                 /* write memory location injecting errors */
 537                                 *i = 0x1122334455667788ULL;
 538                                 __asm__ __volatile__ ("sync");
 539
 540                                 /* disable injects */
 541                                 ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
 542                                 __asm__ __volatile__ ("sync");
 543                                 __asm__ __volatile__ ("isync");
 544
 545                                 /* read data, this generates ECC error */
 546                                 val64 = *i;
 547                                 __asm__ __volatile__ ("sync");
 548
 549                                 /* disable errors for ECC */
 550                                 ddr->err_disable |= ~ECC_ERROR_ENABLE;
 551                                 __asm__ __volatile__ ("sync");
 552                                 __asm__ __volatile__ ("isync");
 553
 554                                 /* re-initialize memory, write the location again
 555                                  * NOT injecting errors this time */
 556                                 *i = 0xcafecafecafecafeULL;
 557                                 __asm__ __volatile__ ("sync");
 558
 559                                 /* enable errors for ECC */
 560                                 ddr->err_disable &= ECC_ERROR_ENABLE;
 561                                 __asm__ __volatile__ ("sync");
 562                                 __asm__ __volatile__ ("isync");
 563                         }
 564
 565                         icache_enable();
 566                         enable_interrupts();
 567
 568                         return 0;
 569                 }
 570         }
 571
 572         printf ("Usage:\n%s\n", cmdtp->usage);
 573         return 1;
 574 }
 575
 576 U_BOOT_CMD(
 577         ecc,     4,     0,      do_ecc,
 578         "ecc     - support for DDR ECC features\n",
 579         "status              - print out status info\n"
 580         "ecc captureclear        - clear capture regs data\n"
 581         "ecc sbecnt <val>        - set Single-Bit Error counter\n"
 582         "ecc sbethr <val>        - set Single-Bit Threshold\n"
 583         "ecc errdisable <flag>   - clear/set disable Memory Error Disable, flag:\n"
 584         "  [-|+]sbe - Single-Bit Error\n"
 585         "  [-|+]mbe - Multiple-Bit Error\n"
 586         "  [-|+]mse - Memory Select Error\n"
 587         "  [-|+]all - all errors\n"
 588         "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
 589         "  mme - Multiple Memory Errors\n"
 590         "  sbe - Single-Bit Error\n"
 591         "  mbe - Multiple-Bit Error\n"
 592         "  mse - Memory Select Error\n"
 593         "  all - all errors\n"
 594         "ecc injectdatahi <hi>  - set Memory Data Path Error Injection Mask High\n"
 595         "ecc injectdatalo <lo>  - set Memory Data Path Error Injection Mask Low\n"
 596         "ecc injectecc <ecc>    - set ECC Error Injection Mask\n"
 597         "ecc inject <en|dis>    - enable/disable error injection\n"
 598         "ecc mirror <en|dis>    - enable/disable mirror byte\n"
 599         "ecc test <addr> <cnt>  - test mem region:\n"
 600         "  - enables injects\n"
 601         "  - writes pattern injecting errors\n"
 602         "  - disables injects\n"
 603         "  - reads pattern back, generates error\n"
 604         "  - re-inits memory"
 605 );
 606 #endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */