git.sur5r.net Git - u-boot/blob - board/mpc8360emds/mpc8360emds.c

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  * based on board/mpc8349emds/mpc8349emds.c
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  */
  15
  16 #include <common.h>
  17 #include <ioports.h>
  18 #include <mpc83xx.h>
  19 #include <i2c.h>
  20 #include <spd.h>
  21 #include <miiphy.h>
  22 #include <command.h>
  23 #if defined(CONFIG_PCI)
  24 #include <pci.h>
  25 #endif
  26 #if defined(CONFIG_SPD_EEPROM)
  27 #include <spd_sdram.h>
  28 #else
  29 #include <asm/mmu.h>
  30 #endif
  31
  32 int board_early_init_f(void)
  33 {
  34         volatile u8 *bcsr = (volatile u8 *)CFG_BCSR;
  35
  36         /* Enable flash write */
  37         bcsr[0xa] &= ~0x04;
  38
  39         return 0;
  40 }
  41
  42 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
  43 extern void ddr_enable_ecc(unsigned int dram_size);
  44 #endif
  45 int fixed_sdram(void);
  46 void sdram_init(void);
  47
  48 long int initdram(int board_type)
  49 {
  50         volatile immap_t *im = (immap_t *) CFG_IMMRBAR;
  51         u32 msize = 0;
  52
  53         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
  54                 return -1;
  55
  56         /* DDR SDRAM - Main SODIMM */
  57         im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
  58 #if defined(CONFIG_SPD_EEPROM)
  59         msize = spd_sdram();
  60 #else
  61         msize = fixed_sdram();
  62 #endif
  63
  64 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
  65         /*
  66          * Initialize DDR ECC byte
  67          */
  68         ddr_enable_ecc(msize * 1024 * 1024);
  69 #endif
  70         /*
  71          * Initialize SDRAM if it is on local bus.
  72          */
  73         sdram_init();
  74         puts("   DDR RAM: ");
  75         /* return total bus SDRAM size(bytes)  -- DDR */
  76         return (msize * 1024 * 1024);
  77 }
  78
  79 #if !defined(CONFIG_SPD_EEPROM)
  80 /*************************************************************************
  81  *  fixed sdram init -- doesn't use serial presence detect.
  82  ************************************************************************/
  83 int fixed_sdram(void)
  84 {
  85         volatile immap_t *im = (immap_t *) CFG_IMMRBAR;
  86         u32 msize = 0;
  87         u32 ddr_size;
  88         u32 ddr_size_log2;
  89
  90         msize = CFG_DDR_SIZE;
  91         for (ddr_size = msize << 20, ddr_size_log2 = 0;
  92              (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
  93                 if (ddr_size & 1) {
  94                         return -1;
  95                 }
  96         }
  97         im->sysconf.ddrlaw[0].ar =
  98             LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
  99 #if (CFG_DDR_SIZE != 256)
 100 #warning Currenly any ddr size other than 256 is not supported
 101 #endif
 102         im->ddr.csbnds[0].csbnds = 0x00000007;
 103         im->ddr.csbnds[1].csbnds = 0x0008000f;
 104
 105         im->ddr.cs_config[0] = CFG_DDR_CONFIG;
 106         im->ddr.cs_config[1] = CFG_DDR_CONFIG;
 107
 108         im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
 109         im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
 110         im->ddr.sdram_cfg = CFG_DDR_CONTROL;
 111
 112         im->ddr.sdram_mode = CFG_DDR_MODE;
 113         im->ddr.sdram_interval = CFG_DDR_INTERVAL;
 114         udelay(200);
 115         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 116
 117         return msize;
 118 }
 119 #endif                          /*!CFG_SPD_EEPROM */
 120
 121 int checkboard(void)
 122 {
 123         puts("Board: Freescale MPC8360EMDS\n");
 124         return 0;
 125 }
 126
 127 /*
 128  * if MPC8360EMDS is soldered with SDRAM
 129  */
 130 #if defined(CFG_BR2_PRELIM)  \
 131         && defined(CFG_OR2_PRELIM) \
 132         && defined(CFG_LBLAWBAR2_PRELIM) \
 133         && defined(CFG_LBLAWAR2_PRELIM)
 134 /*
 135  * Initialize SDRAM memory on the Local Bus.
 136  */
 137
 138 void sdram_init(void)
 139 {
 140         volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
 141         volatile lbus83xx_t *lbc = &immap->lbus;
 142         uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
 143
 144         puts("\n   SDRAM on Local Bus: ");
 145         print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 146         /*
 147          * Setup SDRAM Base and Option Registers, already done in cpu_init.c
 148          */
 149         /*setup mtrpt, lsrt and lbcr for LB bus */
 150         lbc->lbcr = CFG_LBC_LBCR;
 151         lbc->mrtpr = CFG_LBC_MRTPR;
 152         lbc->lsrt = CFG_LBC_LSRT;
 153         asm("sync");
 154
 155         /*
 156          * Configure the SDRAM controller Machine Mode Register.
 157          */
 158         lbc->lsdmr = CFG_LBC_LSDMR_5;   /* Normal Operation */
 159         lbc->lsdmr = CFG_LBC_LSDMR_1;   /* Precharge All Banks */
 160         asm("sync");
 161         *sdram_addr = 0xff;
 162         udelay(100);
 163
 164         /*
 165          * We need do 8 times auto refresh operation.
 166          */
 167         lbc->lsdmr = CFG_LBC_LSDMR_2;
 168         asm("sync");
 169         *sdram_addr = 0xff;     /* 1 times */
 170         udelay(100);
 171         *sdram_addr = 0xff;     /* 2 times */
 172         udelay(100);
 173         *sdram_addr = 0xff;     /* 3 times */
 174         udelay(100);
 175         *sdram_addr = 0xff;     /* 4 times */
 176         udelay(100);
 177         *sdram_addr = 0xff;     /* 5 times */
 178         udelay(100);
 179         *sdram_addr = 0xff;     /* 6 times */
 180         udelay(100);
 181         *sdram_addr = 0xff;     /* 7 times */
 182         udelay(100);
 183         *sdram_addr = 0xff;     /* 8 times */
 184         udelay(100);
 185
 186         /* Mode register write operation */
 187         lbc->lsdmr = CFG_LBC_LSDMR_4;
 188         asm("sync");
 189         *(sdram_addr + 0xcc) = 0xff;
 190         udelay(100);
 191
 192         /* Normal operation */
 193         lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000;
 194         asm("sync");
 195         *sdram_addr = 0xff;
 196         udelay(100);
 197 }
 198 #else
 199 void sdram_init(void)
 200 {
 201         puts("SDRAM on Local Bus is NOT available!\n");
 202 }
 203 #endif
 204
 205 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
 206 /*
 207  * ECC user commands
 208  */
 209 void ecc_print_status(void)
 210 {
 211         volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
 212         volatile ddr83xx_t *ddr = &immap->ddr;
 213
 214         printf("\nECC mode: %s\n\n",
 215                (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
 216
 217         /* Interrupts */
 218         printf("Memory Error Interrupt Enable:\n");
 219         printf("  Multiple-Bit Error Interrupt Enable: %d\n",
 220                (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
 221         printf("  Single-Bit Error Interrupt Enable: %d\n",
 222                (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
 223         printf("  Memory Select Error Interrupt Enable: %d\n\n",
 224                (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
 225
 226         /* Error disable */
 227         printf("Memory Error Disable:\n");
 228         printf("  Multiple-Bit Error Disable: %d\n",
 229                (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
 230         printf("  Sinle-Bit Error Disable: %d\n",
 231                (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
 232         printf("  Memory Select Error Disable: %d\n\n",
 233                (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
 234
 235         /* Error injection */
 236         printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
 237                ddr->data_err_inject_hi, ddr->data_err_inject_lo);
 238
 239         printf("Memory Data Path Error Injection Mask ECC:\n");
 240         printf("  ECC Mirror Byte: %d\n",
 241                (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
 242         printf("  ECC Injection Enable: %d\n",
 243                (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
 244         printf("  ECC Error Injection Mask: 0x%02x\n\n",
 245                ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
 246
 247         /* SBE counter/threshold */
 248         printf("Memory Single-Bit Error Management (0..255):\n");
 249         printf("  Single-Bit Error Threshold: %d\n",
 250                (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
 251         printf("  Single-Bit Error Counter: %d\n\n",
 252                (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
 253
 254         /* Error detect */
 255         printf("Memory Error Detect:\n");
 256         printf("  Multiple Memory Errors: %d\n",
 257                (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
 258         printf("  Multiple-Bit Error: %d\n",
 259                (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
 260         printf("  Single-Bit Error: %d\n",
 261                (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
 262         printf("  Memory Select Error: %d\n\n",
 263                (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
 264
 265         /* Capture data */
 266         printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
 267         printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
 268                ddr->capture_data_hi, ddr->capture_data_lo);
 269         printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
 270                ddr->capture_ecc & CAPTURE_ECC_ECE);
 271
 272         printf("Memory Error Attributes Capture:\n");
 273         printf(" Data Beat Number: %d\n",
 274                (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >>
 275                ECC_CAPT_ATTR_BNUM_SHIFT);
 276         printf("  Transaction Size: %d\n",
 277                (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >>
 278                ECC_CAPT_ATTR_TSIZ_SHIFT);
 279         printf("  Transaction Source: %d\n",
 280                (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >>
 281                ECC_CAPT_ATTR_TSRC_SHIFT);
 282         printf("  Transaction Type: %d\n",
 283                (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >>
 284                ECC_CAPT_ATTR_TTYP_SHIFT);
 285         printf("  Error Information Valid: %d\n\n",
 286                ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
 287 }
 288
 289 int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 290 {
 291         volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
 292         volatile ddr83xx_t *ddr = &immap->ddr;
 293         volatile u32 val;
 294         u64 *addr;
 295         u32 count;
 296         register u64 *i;
 297         u32 ret[2];
 298         u32 pattern[2];
 299         u32 writeback[2];
 300
 301         /* The pattern is written into memory to generate error */
 302         pattern[0] = 0xfedcba98UL;
 303         pattern[1] = 0x76543210UL;
 304
 305         /* After injecting error, re-initialize the memory with the value */
 306         writeback[0] = 0x01234567UL;
 307         writeback[1] = 0x89abcdefUL;
 308
 309         if (argc > 4) {
 310                 printf("Usage:\n%s\n", cmdtp->usage);
 311                 return 1;
 312         }
 313
 314         if (argc == 2) {
 315                 if (strcmp(argv[1], "status") == 0) {
 316                         ecc_print_status();
 317                         return 0;
 318                 } else if (strcmp(argv[1], "captureclear") == 0) {
 319                         ddr->capture_address = 0;
 320                         ddr->capture_data_hi = 0;
 321                         ddr->capture_data_lo = 0;
 322                         ddr->capture_ecc = 0;
 323                         ddr->capture_attributes = 0;
 324                         return 0;
 325                 }
 326         }
 327         if (argc == 3) {
 328                 if (strcmp(argv[1], "sbecnt") == 0) {
 329                         val = simple_strtoul(argv[2], NULL, 10);
 330                         if (val > 255) {
 331                                 printf("Incorrect Counter value, "
 332                                        "should be 0..255\n");
 333                                 return 1;
 334                         }
 335
 336                         val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
 337                         val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
 338
 339                         ddr->err_sbe = val;
 340                         return 0;
 341                 } else if (strcmp(argv[1], "sbethr") == 0) {
 342                         val = simple_strtoul(argv[2], NULL, 10);
 343                         if (val > 255) {
 344                                 printf("Incorrect Counter value, "
 345                                        "should be 0..255\n");
 346                                 return 1;
 347                         }
 348
 349                         val = (val << ECC_ERROR_MAN_SBET_SHIFT);
 350                         val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
 351
 352                         ddr->err_sbe = val;
 353                         return 0;
 354                 } else if (strcmp(argv[1], "errdisable") == 0) {
 355                         val = ddr->err_disable;
 356
 357                         if (strcmp(argv[2], "+sbe") == 0) {
 358                                 val |= ECC_ERROR_DISABLE_SBED;
 359                         } else if (strcmp(argv[2], "+mbe") == 0) {
 360                                 val |= ECC_ERROR_DISABLE_MBED;
 361                         } else if (strcmp(argv[2], "+mse") == 0) {
 362                                 val |= ECC_ERROR_DISABLE_MSED;
 363                         } else if (strcmp(argv[2], "+all") == 0) {
 364                                 val |= (ECC_ERROR_DISABLE_SBED |
 365                                         ECC_ERROR_DISABLE_MBED |
 366                                         ECC_ERROR_DISABLE_MSED);
 367                         } else if (strcmp(argv[2], "-sbe") == 0) {
 368                                 val &= ~ECC_ERROR_DISABLE_SBED;
 369                         } else if (strcmp(argv[2], "-mbe") == 0) {
 370                                 val &= ~ECC_ERROR_DISABLE_MBED;
 371                         } else if (strcmp(argv[2], "-mse") == 0) {
 372                                 val &= ~ECC_ERROR_DISABLE_MSED;
 373                         } else if (strcmp(argv[2], "-all") == 0) {
 374                                 val &= ~(ECC_ERROR_DISABLE_SBED |
 375                                          ECC_ERROR_DISABLE_MBED |
 376                                          ECC_ERROR_DISABLE_MSED);
 377                         } else {
 378                                 printf("Incorrect err_disable field\n");
 379                                 return 1;
 380                         }
 381
 382                         ddr->err_disable = val;
 383                         __asm__ __volatile__("sync");
 384                         __asm__ __volatile__("isync");
 385                         return 0;
 386                 } else if (strcmp(argv[1], "errdetectclr") == 0) {
 387                         val = ddr->err_detect;
 388
 389                         if (strcmp(argv[2], "mme") == 0) {
 390                                 val |= ECC_ERROR_DETECT_MME;
 391                         } else if (strcmp(argv[2], "sbe") == 0) {
 392                                 val |= ECC_ERROR_DETECT_SBE;
 393                         } else if (strcmp(argv[2], "mbe") == 0) {
 394                                 val |= ECC_ERROR_DETECT_MBE;
 395                         } else if (strcmp(argv[2], "mse") == 0) {
 396                                 val |= ECC_ERROR_DETECT_MSE;
 397                         } else if (strcmp(argv[2], "all") == 0) {
 398                                 val |= (ECC_ERROR_DETECT_MME |
 399                                         ECC_ERROR_DETECT_MBE |
 400                                         ECC_ERROR_DETECT_SBE |
 401                                         ECC_ERROR_DETECT_MSE);
 402                         } else {
 403                                 printf("Incorrect err_detect field\n");
 404                                 return 1;
 405                         }
 406
 407                         ddr->err_detect = val;
 408                         return 0;
 409                 } else if (strcmp(argv[1], "injectdatahi") == 0) {
 410                         val = simple_strtoul(argv[2], NULL, 16);
 411
 412                         ddr->data_err_inject_hi = val;
 413                         return 0;
 414                 } else if (strcmp(argv[1], "injectdatalo") == 0) {
 415                         val = simple_strtoul(argv[2], NULL, 16);
 416
 417                         ddr->data_err_inject_lo = val;
 418                         return 0;
 419                 } else if (strcmp(argv[1], "injectecc") == 0) {
 420                         val = simple_strtoul(argv[2], NULL, 16);
 421                         if (val > 0xff) {
 422                                 printf("Incorrect ECC inject mask, "
 423                                        "should be 0x00..0xff\n");
 424                                 return 1;
 425                         }
 426                         val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
 427
 428                         ddr->ecc_err_inject = val;
 429                         return 0;
 430                 } else if (strcmp(argv[1], "inject") == 0) {
 431                         val = ddr->ecc_err_inject;
 432
 433                         if (strcmp(argv[2], "en") == 0)
 434                                 val |= ECC_ERR_INJECT_EIEN;
 435                         else if (strcmp(argv[2], "dis") == 0)
 436                                 val &= ~ECC_ERR_INJECT_EIEN;
 437                         else
 438                                 printf("Incorrect command\n");
 439
 440                         ddr->ecc_err_inject = val;
 441                         __asm__ __volatile__("sync");
 442                         __asm__ __volatile__("isync");
 443                         return 0;
 444                 } else if (strcmp(argv[1], "mirror") == 0) {
 445                         val = ddr->ecc_err_inject;
 446
 447                         if (strcmp(argv[2], "en") == 0)
 448                                 val |= ECC_ERR_INJECT_EMB;
 449                         else if (strcmp(argv[2], "dis") == 0)
 450                                 val &= ~ECC_ERR_INJECT_EMB;
 451                         else
 452                                 printf("Incorrect command\n");
 453
 454                         ddr->ecc_err_inject = val;
 455                         return 0;
 456                 }
 457         }
 458         if (argc == 4) {
 459                 if (strcmp(argv[1], "testdw") == 0) {
 460                         addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
 461                         count = simple_strtoul(argv[3], NULL, 16);
 462
 463                         if ((u32) addr % 8) {
 464                                 printf("Address not alligned on "
 465                                        "double word boundary\n");
 466                                 return 1;
 467                         }
 468                         disable_interrupts();
 469
 470                         for (i = addr; i < addr + count; i++) {
 471
 472                                 /* enable injects */
 473                                 ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
 474                                 __asm__ __volatile__("sync");
 475                                 __asm__ __volatile__("isync");
 476
 477                                 /* write memory location injecting errors */
 478                                 ppcDWstore((u32 *) i, pattern);
 479
 480                                 /* disable injects */
 481                                 ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
 482                                 __asm__ __volatile__("sync");
 483                                 __asm__ __volatile__("isync");
 484
 485                                 /* read data, this generates ECC error */
 486                                 ppcDWload((u32 *) i, ret);
 487
 488                                 /* re-initialize memory, double word write the location again,
 489                                  * generates new ECC code this time */
 490                                 ppcDWstore((u32 *) i, writeback);
 491                         }
 492                         enable_interrupts();
 493                         return 0;
 494                 }
 495                 if (strcmp(argv[1], "testword") == 0) {
 496                         addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
 497                         count = simple_strtoul(argv[3], NULL, 16);
 498
 499                         if ((u32) addr % 8) {
 500                                 printf("Address not alligned on "
 501                                        "double word boundary\n");
 502                                 return 1;
 503                         }
 504                         disable_interrupts();
 505
 506                         for (i = addr; i < addr + count; i++) {
 507
 508                                 /* enable injects */
 509                                 ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
 510                                 __asm__ __volatile__("sync");
 511                                 __asm__ __volatile__("isync");
 512
 513                                 /* write memory location injecting errors */
 514                                 *(u32 *) i = 0xfedcba98UL;
 515                                 __asm__ __volatile__("sync");
 516
 517                                 /* sub double word write,
 518                                  * bus will read-modify-write,
 519                                  * generates ECC error */
 520                                 *((u32 *) i + 1) = 0x76543210UL;
 521                                 __asm__ __volatile__("sync");
 522
 523                                 /* disable injects */
 524                                 ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
 525                                 __asm__ __volatile__("sync");
 526                                 __asm__ __volatile__("isync");
 527
 528                                 /* re-initialize memory,
 529                                  * double word write the location again,
 530                                  * generates new ECC code this time */
 531                                 ppcDWstore((u32 *) i, writeback);
 532                         }
 533                         enable_interrupts();
 534                         return 0;
 535                 }
 536         }
 537         printf("Usage:\n%s\n", cmdtp->usage);
 538         return 1;
 539 }
 540
 541 U_BOOT_CMD(ecc, 4, 0, do_ecc,
 542            "ecc     - support for DDR ECC features\n",
 543            "status              - print out status info\n"
 544            "ecc captureclear        - clear capture regs data\n"
 545            "ecc sbecnt <val>        - set Single-Bit Error counter\n"
 546            "ecc sbethr <val>        - set Single-Bit Threshold\n"
 547            "ecc errdisable <flag>   - clear/set disable Memory Error Disable, flag:\n"
 548            "  [-|+]sbe - Single-Bit Error\n"
 549            "  [-|+]mbe - Multiple-Bit Error\n"
 550            "  [-|+]mse - Memory Select Error\n"
 551            "  [-|+]all - all errors\n"
 552            "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
 553            "  mme - Multiple Memory Errors\n"
 554            "  sbe - Single-Bit Error\n"
 555            "  mbe - Multiple-Bit Error\n"
 556            "  mse - Memory Select Error\n"
 557            "  all - all errors\n"
 558            "ecc injectdatahi <hi>  - set Memory Data Path Error Injection Mask High\n"
 559            "ecc injectdatalo <lo>  - set Memory Data Path Error Injection Mask Low\n"
 560            "ecc injectecc <ecc>    - set ECC Error Injection Mask\n"
 561            "ecc inject <en|dis>    - enable/disable error injection\n"
 562            "ecc mirror <en|dis>    - enable/disable mirror byte\n"
 563            "ecc testdw <addr> <cnt>  - test mem region with double word access:\n"
 564            "  - enables injects\n"
 565            "  - writes pattern injecting errors with double word access\n"
 566            "  - disables injects\n"
 567            "  - reads pattern back with double word access, generates error\n"
 568            "  - re-inits memory\n"
 569            "ecc testword <addr> <cnt>  - test mem region with word access:\n"
 570            "  - enables injects\n"
 571            "  - writes pattern injecting errors with word access\n"
 572            "  - writes pattern with word access, generates error\n"
 573            "  - disables injects\n" "  - re-inits memory");
 574 #endif                          /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */