git.sur5r.net Git - u-boot/blob - board/mpc8360emds/mpc8360emds.c

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  * based on board/mpc8349emds/mpc8349emds.c
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  */
  15
  16 #include <common.h>
  17 #include <ioports.h>
  18 #include <mpc83xx.h>
  19 #include <i2c.h>
  20 #include <spd.h>
  21 #include <miiphy.h>
  22 #include <command.h>
  23 #if defined(CONFIG_PCI)
  24 #include <pci.h>
  25 #endif
  26 #if defined(CONFIG_SPD_EEPROM)
  27 #include <spd_sdram.h>
  28 #else
  29 #include <asm/mmu.h>
  30 #endif
  31 #if defined(CONFIG_OF_FLAT_TREE)
  32 #include <ft_build.h>
  33 #endif
  34
  35 const qe_iop_conf_t qe_iop_conf_tab[] = {
  36         /* GETH1 */
  37         {0,  3, 1, 0, 1}, /* TxD0 */
  38         {0,  4, 1, 0, 1}, /* TxD1 */
  39         {0,  5, 1, 0, 1}, /* TxD2 */
  40         {0,  6, 1, 0, 1}, /* TxD3 */
  41         {1,  6, 1, 0, 3}, /* TxD4 */
  42         {1,  7, 1, 0, 1}, /* TxD5 */
  43         {1,  9, 1, 0, 2}, /* TxD6 */
  44         {1, 10, 1, 0, 2}, /* TxD7 */
  45         {0,  9, 2, 0, 1}, /* RxD0 */
  46         {0, 10, 2, 0, 1}, /* RxD1 */
  47         {0, 11, 2, 0, 1}, /* RxD2 */
  48         {0, 12, 2, 0, 1}, /* RxD3 */
  49         {0, 13, 2, 0, 1}, /* RxD4 */
  50         {1,  1, 2, 0, 2}, /* RxD5 */
  51         {1,  0, 2, 0, 2}, /* RxD6 */
  52         {1,  4, 2, 0, 2}, /* RxD7 */
  53         {0,  7, 1, 0, 1}, /* TX_EN */
  54         {0,  8, 1, 0, 1}, /* TX_ER */
  55         {0, 15, 2, 0, 1}, /* RX_DV */
  56         {0, 16, 2, 0, 1}, /* RX_ER */
  57         {0,  0, 2, 0, 1}, /* RX_CLK */
  58         {2,  9, 1, 0, 3}, /* GTX_CLK - CLK10 */
  59         {2,  8, 2, 0, 1}, /* GTX125 - CLK9 */
  60         /* GETH2 */
  61         {0, 17, 1, 0, 1}, /* TxD0 */
  62         {0, 18, 1, 0, 1}, /* TxD1 */
  63         {0, 19, 1, 0, 1}, /* TxD2 */
  64         {0, 20, 1, 0, 1}, /* TxD3 */
  65         {1,  2, 1, 0, 1}, /* TxD4 */
  66         {1,  3, 1, 0, 2}, /* TxD5 */
  67         {1,  5, 1, 0, 3}, /* TxD6 */
  68         {1,  8, 1, 0, 3}, /* TxD7 */
  69         {0, 23, 2, 0, 1}, /* RxD0 */
  70         {0, 24, 2, 0, 1}, /* RxD1 */
  71         {0, 25, 2, 0, 1}, /* RxD2 */
  72         {0, 26, 2, 0, 1}, /* RxD3 */
  73         {0, 27, 2, 0, 1}, /* RxD4 */
  74         {1, 12, 2, 0, 2}, /* RxD5 */
  75         {1, 13, 2, 0, 3}, /* RxD6 */
  76         {1, 11, 2, 0, 2}, /* RxD7 */
  77         {0, 21, 1, 0, 1}, /* TX_EN */
  78         {0, 22, 1, 0, 1}, /* TX_ER */
  79         {0, 29, 2, 0, 1}, /* RX_DV */
  80         {0, 30, 2, 0, 1}, /* RX_ER */
  81         {0, 31, 2, 0, 1}, /* RX_CLK */
  82         {2,  2, 1, 0, 2}, /* GTX_CLK = CLK10 */
  83         {2,  3, 2, 0, 1}, /* GTX125 - CLK4 */
  84
  85         {0,  1, 3, 0, 2}, /* MDIO */
  86         {0,  2, 1, 0, 1}, /* MDC */
  87
  88         {0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
  89 };
  90
  91 int board_early_init_f(void)
  92 {
  93         volatile u8 *bcsr = (volatile u8 *)CFG_BCSR;
  94
  95         /* Enable flash write */
  96         bcsr[0xa] &= ~0x04;
  97
  98         return 0;
  99 }
 100
 101 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
 102 extern void ddr_enable_ecc(unsigned int dram_size);
 103 #endif
 104 int fixed_sdram(void);
 105 void sdram_init(void);
 106
 107 long int initdram(int board_type)
 108 {
 109         volatile immap_t *im = (immap_t *) CFG_IMMR;
 110         u32 msize = 0;
 111
 112         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 113                 return -1;
 114
 115         /* DDR SDRAM - Main SODIMM */
 116         im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
 117 #if defined(CONFIG_SPD_EEPROM)
 118         msize = spd_sdram();
 119 #else
 120         msize = fixed_sdram();
 121 #endif
 122
 123 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
 124         /*
 125          * Initialize DDR ECC byte
 126          */
 127         ddr_enable_ecc(msize * 1024 * 1024);
 128 #endif
 129         /*
 130          * Initialize SDRAM if it is on local bus.
 131          */
 132         sdram_init();
 133         puts("   DDR RAM: ");
 134         /* return total bus SDRAM size(bytes)  -- DDR */
 135         return (msize * 1024 * 1024);
 136 }
 137
 138 #if !defined(CONFIG_SPD_EEPROM)
 139 /*************************************************************************
 140  *  fixed sdram init -- doesn't use serial presence detect.
 141  ************************************************************************/
 142 int fixed_sdram(void)
 143 {
 144         volatile immap_t *im = (immap_t *) CFG_IMMR;
 145         u32 msize = 0;
 146         u32 ddr_size;
 147         u32 ddr_size_log2;
 148
 149         msize = CFG_DDR_SIZE;
 150         for (ddr_size = msize << 20, ddr_size_log2 = 0;
 151              (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
 152                 if (ddr_size & 1) {
 153                         return -1;
 154                 }
 155         }
 156         im->sysconf.ddrlaw[0].ar =
 157             LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 158 #if (CFG_DDR_SIZE != 256)
 159 #warning Currenly any ddr size other than 256 is not supported
 160 #endif
 161 #ifdef CONFIG_DDR_II
 162         im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
 163         im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
 164         im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
 165         im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
 166         im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
 167         im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
 168         im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
 169         im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
 170         im->ddr.sdram_mode = CFG_DDR_MODE;
 171         im->ddr.sdram_mode2 = CFG_DDR_MODE2;
 172         im->ddr.sdram_interval = CFG_DDR_INTERVAL;
 173         im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
 174 #else
 175         im->ddr.csbnds[0].csbnds = 0x00000007;
 176         im->ddr.csbnds[1].csbnds = 0x0008000f;
 177
 178         im->ddr.cs_config[0] = CFG_DDR_CONFIG;
 179         im->ddr.cs_config[1] = CFG_DDR_CONFIG;
 180
 181         im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
 182         im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
 183         im->ddr.sdram_cfg = CFG_DDR_CONTROL;
 184
 185         im->ddr.sdram_mode = CFG_DDR_MODE;
 186         im->ddr.sdram_interval = CFG_DDR_INTERVAL;
 187 #endif
 188         udelay(200);
 189         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 190
 191         return msize;
 192 }
 193 #endif                          /*!CFG_SPD_EEPROM */
 194
 195 int checkboard(void)
 196 {
 197         puts("Board: Freescale MPC8360EMDS\n");
 198         return 0;
 199 }
 200
 201 /*
 202  * if MPC8360EMDS is soldered with SDRAM
 203  */
 204 #if defined(CFG_BR2_PRELIM)  \
 205         && defined(CFG_OR2_PRELIM) \
 206         && defined(CFG_LBLAWBAR2_PRELIM) \
 207         && defined(CFG_LBLAWAR2_PRELIM)
 208 /*
 209  * Initialize SDRAM memory on the Local Bus.
 210  */
 211
 212 void sdram_init(void)
 213 {
 214         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 215         volatile lbus83xx_t *lbc = &immap->lbus;
 216         uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
 217
 218         puts("\n   SDRAM on Local Bus: ");
 219         print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 220         /*
 221          * Setup SDRAM Base and Option Registers, already done in cpu_init.c
 222          */
 223         /*setup mtrpt, lsrt and lbcr for LB bus */
 224         lbc->lbcr = CFG_LBC_LBCR;
 225         lbc->mrtpr = CFG_LBC_MRTPR;
 226         lbc->lsrt = CFG_LBC_LSRT;
 227         asm("sync");
 228
 229         /*
 230          * Configure the SDRAM controller Machine Mode Register.
 231          */
 232         lbc->lsdmr = CFG_LBC_LSDMR_5;   /* Normal Operation */
 233         lbc->lsdmr = CFG_LBC_LSDMR_1;   /* Precharge All Banks */
 234         asm("sync");
 235         *sdram_addr = 0xff;
 236         udelay(100);
 237
 238         /*
 239          * We need do 8 times auto refresh operation.
 240          */
 241         lbc->lsdmr = CFG_LBC_LSDMR_2;
 242         asm("sync");
 243         *sdram_addr = 0xff;     /* 1 times */
 244         udelay(100);
 245         *sdram_addr = 0xff;     /* 2 times */
 246         udelay(100);
 247         *sdram_addr = 0xff;     /* 3 times */
 248         udelay(100);
 249         *sdram_addr = 0xff;     /* 4 times */
 250         udelay(100);
 251         *sdram_addr = 0xff;     /* 5 times */
 252         udelay(100);
 253         *sdram_addr = 0xff;     /* 6 times */
 254         udelay(100);
 255         *sdram_addr = 0xff;     /* 7 times */
 256         udelay(100);
 257         *sdram_addr = 0xff;     /* 8 times */
 258         udelay(100);
 259
 260         /* Mode register write operation */
 261         lbc->lsdmr = CFG_LBC_LSDMR_4;
 262         asm("sync");
 263         *(sdram_addr + 0xcc) = 0xff;
 264         udelay(100);
 265
 266         /* Normal operation */
 267         lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000;
 268         asm("sync");
 269         *sdram_addr = 0xff;
 270         udelay(100);
 271 }
 272 #else
 273 void sdram_init(void)
 274 {
 275         puts("SDRAM on Local Bus is NOT available!\n");
 276 }
 277 #endif
 278
 279 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
 280 /*
 281  * ECC user commands
 282  */
 283 void ecc_print_status(void)
 284 {
 285         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 286         volatile ddr83xx_t *ddr = &immap->ddr;
 287
 288         printf("\nECC mode: %s\n\n",
 289                (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
 290
 291         /* Interrupts */
 292         printf("Memory Error Interrupt Enable:\n");
 293         printf("  Multiple-Bit Error Interrupt Enable: %d\n",
 294                (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
 295         printf("  Single-Bit Error Interrupt Enable: %d\n",
 296                (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
 297         printf("  Memory Select Error Interrupt Enable: %d\n\n",
 298                (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
 299
 300         /* Error disable */
 301         printf("Memory Error Disable:\n");
 302         printf("  Multiple-Bit Error Disable: %d\n",
 303                (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
 304         printf("  Sinle-Bit Error Disable: %d\n",
 305                (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
 306         printf("  Memory Select Error Disable: %d\n\n",
 307                (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
 308
 309         /* Error injection */
 310         printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
 311                ddr->data_err_inject_hi, ddr->data_err_inject_lo);
 312
 313         printf("Memory Data Path Error Injection Mask ECC:\n");
 314         printf("  ECC Mirror Byte: %d\n",
 315                (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
 316         printf("  ECC Injection Enable: %d\n",
 317                (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
 318         printf("  ECC Error Injection Mask: 0x%02x\n\n",
 319                ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
 320
 321         /* SBE counter/threshold */
 322         printf("Memory Single-Bit Error Management (0..255):\n");
 323         printf("  Single-Bit Error Threshold: %d\n",
 324                (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
 325         printf("  Single-Bit Error Counter: %d\n\n",
 326                (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
 327
 328         /* Error detect */
 329         printf("Memory Error Detect:\n");
 330         printf("  Multiple Memory Errors: %d\n",
 331                (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
 332         printf("  Multiple-Bit Error: %d\n",
 333                (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
 334         printf("  Single-Bit Error: %d\n",
 335                (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
 336         printf("  Memory Select Error: %d\n\n",
 337                (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
 338
 339         /* Capture data */
 340         printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
 341         printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
 342                ddr->capture_data_hi, ddr->capture_data_lo);
 343         printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
 344                ddr->capture_ecc & CAPTURE_ECC_ECE);
 345
 346         printf("Memory Error Attributes Capture:\n");
 347         printf(" Data Beat Number: %d\n",
 348                (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >>
 349                ECC_CAPT_ATTR_BNUM_SHIFT);
 350         printf("  Transaction Size: %d\n",
 351                (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >>
 352                ECC_CAPT_ATTR_TSIZ_SHIFT);
 353         printf("  Transaction Source: %d\n",
 354                (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >>
 355                ECC_CAPT_ATTR_TSRC_SHIFT);
 356         printf("  Transaction Type: %d\n",
 357                (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >>
 358                ECC_CAPT_ATTR_TTYP_SHIFT);
 359         printf("  Error Information Valid: %d\n\n",
 360                ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
 361 }
 362
 363 int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 364 {
 365         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 366         volatile ddr83xx_t *ddr = &immap->ddr;
 367         volatile u32 val;
 368         u64 *addr;
 369         u32 count;
 370         register u64 *i;
 371         u32 ret[2];
 372         u32 pattern[2];
 373         u32 writeback[2];
 374
 375         /* The pattern is written into memory to generate error */
 376         pattern[0] = 0xfedcba98UL;
 377         pattern[1] = 0x76543210UL;
 378
 379         /* After injecting error, re-initialize the memory with the value */
 380         writeback[0] = 0x01234567UL;
 381         writeback[1] = 0x89abcdefUL;
 382
 383         if (argc > 4) {
 384                 printf("Usage:\n%s\n", cmdtp->usage);
 385                 return 1;
 386         }
 387
 388         if (argc == 2) {
 389                 if (strcmp(argv[1], "status") == 0) {
 390                         ecc_print_status();
 391                         return 0;
 392                 } else if (strcmp(argv[1], "captureclear") == 0) {
 393                         ddr->capture_address = 0;
 394                         ddr->capture_data_hi = 0;
 395                         ddr->capture_data_lo = 0;
 396                         ddr->capture_ecc = 0;
 397                         ddr->capture_attributes = 0;
 398                         return 0;
 399                 }
 400         }
 401         if (argc == 3) {
 402                 if (strcmp(argv[1], "sbecnt") == 0) {
 403                         val = simple_strtoul(argv[2], NULL, 10);
 404                         if (val > 255) {
 405                                 printf("Incorrect Counter value, "
 406                                        "should be 0..255\n");
 407                                 return 1;
 408                         }
 409
 410                         val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
 411                         val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
 412
 413                         ddr->err_sbe = val;
 414                         return 0;
 415                 } else if (strcmp(argv[1], "sbethr") == 0) {
 416                         val = simple_strtoul(argv[2], NULL, 10);
 417                         if (val > 255) {
 418                                 printf("Incorrect Counter value, "
 419                                        "should be 0..255\n");
 420                                 return 1;
 421                         }
 422
 423                         val = (val << ECC_ERROR_MAN_SBET_SHIFT);
 424                         val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
 425
 426                         ddr->err_sbe = val;
 427                         return 0;
 428                 } else if (strcmp(argv[1], "errdisable") == 0) {
 429                         val = ddr->err_disable;
 430
 431                         if (strcmp(argv[2], "+sbe") == 0) {
 432                                 val |= ECC_ERROR_DISABLE_SBED;
 433                         } else if (strcmp(argv[2], "+mbe") == 0) {
 434                                 val |= ECC_ERROR_DISABLE_MBED;
 435                         } else if (strcmp(argv[2], "+mse") == 0) {
 436                                 val |= ECC_ERROR_DISABLE_MSED;
 437                         } else if (strcmp(argv[2], "+all") == 0) {
 438                                 val |= (ECC_ERROR_DISABLE_SBED |
 439                                         ECC_ERROR_DISABLE_MBED |
 440                                         ECC_ERROR_DISABLE_MSED);
 441                         } else if (strcmp(argv[2], "-sbe") == 0) {
 442                                 val &= ~ECC_ERROR_DISABLE_SBED;
 443                         } else if (strcmp(argv[2], "-mbe") == 0) {
 444                                 val &= ~ECC_ERROR_DISABLE_MBED;
 445                         } else if (strcmp(argv[2], "-mse") == 0) {
 446                                 val &= ~ECC_ERROR_DISABLE_MSED;
 447                         } else if (strcmp(argv[2], "-all") == 0) {
 448                                 val &= ~(ECC_ERROR_DISABLE_SBED |
 449                                          ECC_ERROR_DISABLE_MBED |
 450                                          ECC_ERROR_DISABLE_MSED);
 451                         } else {
 452                                 printf("Incorrect err_disable field\n");
 453                                 return 1;
 454                         }
 455
 456                         ddr->err_disable = val;
 457                         __asm__ __volatile__("sync");
 458                         __asm__ __volatile__("isync");
 459                         return 0;
 460                 } else if (strcmp(argv[1], "errdetectclr") == 0) {
 461                         val = ddr->err_detect;
 462
 463                         if (strcmp(argv[2], "mme") == 0) {
 464                                 val |= ECC_ERROR_DETECT_MME;
 465                         } else if (strcmp(argv[2], "sbe") == 0) {
 466                                 val |= ECC_ERROR_DETECT_SBE;
 467                         } else if (strcmp(argv[2], "mbe") == 0) {
 468                                 val |= ECC_ERROR_DETECT_MBE;
 469                         } else if (strcmp(argv[2], "mse") == 0) {
 470                                 val |= ECC_ERROR_DETECT_MSE;
 471                         } else if (strcmp(argv[2], "all") == 0) {
 472                                 val |= (ECC_ERROR_DETECT_MME |
 473                                         ECC_ERROR_DETECT_MBE |
 474                                         ECC_ERROR_DETECT_SBE |
 475                                         ECC_ERROR_DETECT_MSE);
 476                         } else {
 477                                 printf("Incorrect err_detect field\n");
 478                                 return 1;
 479                         }
 480
 481                         ddr->err_detect = val;
 482                         return 0;
 483                 } else if (strcmp(argv[1], "injectdatahi") == 0) {
 484                         val = simple_strtoul(argv[2], NULL, 16);
 485
 486                         ddr->data_err_inject_hi = val;
 487                         return 0;
 488                 } else if (strcmp(argv[1], "injectdatalo") == 0) {
 489                         val = simple_strtoul(argv[2], NULL, 16);
 490
 491                         ddr->data_err_inject_lo = val;
 492                         return 0;
 493                 } else if (strcmp(argv[1], "injectecc") == 0) {
 494                         val = simple_strtoul(argv[2], NULL, 16);
 495                         if (val > 0xff) {
 496                                 printf("Incorrect ECC inject mask, "
 497                                        "should be 0x00..0xff\n");
 498                                 return 1;
 499                         }
 500                         val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
 501
 502                         ddr->ecc_err_inject = val;
 503                         return 0;
 504                 } else if (strcmp(argv[1], "inject") == 0) {
 505                         val = ddr->ecc_err_inject;
 506
 507                         if (strcmp(argv[2], "en") == 0)
 508                                 val |= ECC_ERR_INJECT_EIEN;
 509                         else if (strcmp(argv[2], "dis") == 0)
 510                                 val &= ~ECC_ERR_INJECT_EIEN;
 511                         else
 512                                 printf("Incorrect command\n");
 513
 514                         ddr->ecc_err_inject = val;
 515                         __asm__ __volatile__("sync");
 516                         __asm__ __volatile__("isync");
 517                         return 0;
 518                 } else if (strcmp(argv[1], "mirror") == 0) {
 519                         val = ddr->ecc_err_inject;
 520
 521                         if (strcmp(argv[2], "en") == 0)
 522                                 val |= ECC_ERR_INJECT_EMB;
 523                         else if (strcmp(argv[2], "dis") == 0)
 524                                 val &= ~ECC_ERR_INJECT_EMB;
 525                         else
 526                                 printf("Incorrect command\n");
 527
 528                         ddr->ecc_err_inject = val;
 529                         return 0;
 530                 }
 531         }
 532         if (argc == 4) {
 533                 if (strcmp(argv[1], "testdw") == 0) {
 534                         addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
 535                         count = simple_strtoul(argv[3], NULL, 16);
 536
 537                         if ((u32) addr % 8) {
 538                                 printf("Address not alligned on "
 539                                        "double word boundary\n");
 540                                 return 1;
 541                         }
 542                         disable_interrupts();
 543
 544                         for (i = addr; i < addr + count; i++) {
 545
 546                                 /* enable injects */
 547                                 ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
 548                                 __asm__ __volatile__("sync");
 549                                 __asm__ __volatile__("isync");
 550
 551                                 /* write memory location injecting errors */
 552                                 ppcDWstore((u32 *) i, pattern);
 553                                 __asm__ __volatile__("sync");
 554
 555                                 /* disable injects */
 556                                 ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
 557                                 __asm__ __volatile__("sync");
 558                                 __asm__ __volatile__("isync");
 559
 560                                 /* read data, this generates ECC error */
 561                                 ppcDWload((u32 *) i, ret);
 562                                 __asm__ __volatile__("sync");
 563
 564                                 /* re-initialize memory, double word write the location again,
 565                                  * generates new ECC code this time */
 566                                 ppcDWstore((u32 *) i, writeback);
 567                                 __asm__ __volatile__("sync");
 568                         }
 569                         enable_interrupts();
 570                         return 0;
 571                 }
 572                 if (strcmp(argv[1], "testword") == 0) {
 573                         addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
 574                         count = simple_strtoul(argv[3], NULL, 16);
 575
 576                         if ((u32) addr % 8) {
 577                                 printf("Address not alligned on "
 578                                        "double word boundary\n");
 579                                 return 1;
 580                         }
 581                         disable_interrupts();
 582
 583                         for (i = addr; i < addr + count; i++) {
 584
 585                                 /* enable injects */
 586                                 ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
 587                                 __asm__ __volatile__("sync");
 588                                 __asm__ __volatile__("isync");
 589
 590                                 /* write memory location injecting errors */
 591                                 *(u32 *) i = 0xfedcba98UL;
 592                                 __asm__ __volatile__("sync");
 593
 594                                 /* sub double word write,
 595                                  * bus will read-modify-write,
 596                                  * generates ECC error */
 597                                 *((u32 *) i + 1) = 0x76543210UL;
 598                                 __asm__ __volatile__("sync");
 599
 600                                 /* disable injects */
 601                                 ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
 602                                 __asm__ __volatile__("sync");
 603                                 __asm__ __volatile__("isync");
 604
 605                                 /* re-initialize memory,
 606                                  * double word write the location again,
 607                                  * generates new ECC code this time */
 608                                 ppcDWstore((u32 *) i, writeback);
 609                                 __asm__ __volatile__("sync");
 610                         }
 611                         enable_interrupts();
 612                         return 0;
 613                 }
 614         }
 615         printf("Usage:\n%s\n", cmdtp->usage);
 616         return 1;
 617 }
 618
 619 U_BOOT_CMD(ecc, 4, 0, do_ecc,
 620            "ecc     - support for DDR ECC features\n",
 621            "status              - print out status info\n"
 622            "ecc captureclear        - clear capture regs data\n"
 623            "ecc sbecnt <val>        - set Single-Bit Error counter\n"
 624            "ecc sbethr <val>        - set Single-Bit Threshold\n"
 625            "ecc errdisable <flag>   - clear/set disable Memory Error Disable, flag:\n"
 626            "  [-|+]sbe - Single-Bit Error\n"
 627            "  [-|+]mbe - Multiple-Bit Error\n"
 628            "  [-|+]mse - Memory Select Error\n"
 629            "  [-|+]all - all errors\n"
 630            "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
 631            "  mme - Multiple Memory Errors\n"
 632            "  sbe - Single-Bit Error\n"
 633            "  mbe - Multiple-Bit Error\n"
 634            "  mse - Memory Select Error\n"
 635            "  all - all errors\n"
 636            "ecc injectdatahi <hi>  - set Memory Data Path Error Injection Mask High\n"
 637            "ecc injectdatalo <lo>  - set Memory Data Path Error Injection Mask Low\n"
 638            "ecc injectecc <ecc>    - set ECC Error Injection Mask\n"
 639            "ecc inject <en|dis>    - enable/disable error injection\n"
 640            "ecc mirror <en|dis>    - enable/disable mirror byte\n"
 641            "ecc testdw <addr> <cnt>  - test mem region with double word access:\n"
 642            "  - enables injects\n"
 643            "  - writes pattern injecting errors with double word access\n"
 644            "  - disables injects\n"
 645            "  - reads pattern back with double word access, generates error\n"
 646            "  - re-inits memory\n"
 647            "ecc testword <addr> <cnt>  - test mem region with word access:\n"
 648            "  - enables injects\n"
 649            "  - writes pattern injecting errors with word access\n"
 650            "  - writes pattern with word access, generates error\n"
 651            "  - disables injects\n" "  - re-inits memory");
 652 #endif                          /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
 653
 654 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
 655 void
 656 ft_board_setup(void *blob, bd_t *bd)
 657 {
 658         u32 *p;
 659         int len;
 660
 661 #ifdef CONFIG_PCI
 662         ft_pci_setup(blob, bd);
 663 #endif
 664         ft_cpu_setup(blob, bd);
 665
 666         p = ft_get_prop(blob, "/memory/reg", &len);
 667         if (p != NULL) {
 668                 *p++ = cpu_to_be32(bd->bi_memstart);
 669                 *p = cpu_to_be32(bd->bi_memsize);
 670         }
 671 }
 672 #endif